mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge tag 'arm-soc/for-4.5/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
Merge "Broadcom devicetree-arm64 changes for v4.5" from Florian Fainelli: This pull request contains Broadcom ARM64-based Device Tree changes: - Anup Patel adds L2 cache, SMMU, syscon-based reboot, PMU v3, iProc RNG200 (HWRNG) and NAND flash controller support to the Northstar 2 SoCs - Ray Jui adds the I2C Device Tree nodes to the Norsthar 2 SoCs - Jon Mason enables the clock providers on the Norsthar 2 SoCs * tag 'arm-soc/for-4.5/devicetree-arm64' of http://github.com/Broadcom/stblinux: ARM64: dts: enable clock support for Broadcom NS2 arm64: dts: Add BRCM IPROC NAND DT node for NS2 arm64: dts: Add I2C nodes for NS2 arm64: dts: Add IPROC RNG200 DT node for NS2 arm64: dts: Add ARM PMUv3 DT node in NS2 DT arm64: dts: Add syscon based reboot in DT for NS2 arm64: dts: Add SMMU DT node for NS2 arm64: dts: Add L2-cache DT node for NS2
This commit is contained in:
Arnd Bergmann
commit
8b9a3fde5a
@ -50,10 +50,28 @@ memory {
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device_type = "memory";
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reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
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};
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};
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soc: soc {
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uart3: serial@66130000 {
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status = "ok";
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};
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&i2c0 {
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status = "ok";
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};
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&i2c1 {
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status = "ok";
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};
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&uart3 {
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status = "ok";
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};
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&nand {
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nandcs@0 {
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compatible = "brcm,nandcs";
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reg = <0>;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <8>;
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nand-ecc-step-size = <512>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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@ -31,6 +31,7 @@
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/bcm-ns2.h>
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/memreserve/ 0x84b00000 0x00000008;
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@ -44,36 +45,44 @@ cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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A57_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x84b00000>;
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next-level-cache = <&CLUSTER0_L2>;
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};
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cpu@1 {
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A57_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x84b00000>;
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next-level-cache = <&CLUSTER0_L2>;
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};
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cpu@2 {
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A57_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 2>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x84b00000>;
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next-level-cache = <&CLUSTER0_L2>;
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};
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cpu@3 {
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A57_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 3>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x84b00000>;
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next-level-cache = <&CLUSTER0_L2>;
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};
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CLUSTER0_L2: l2-cache@000 {
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compatible = "cache";
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};
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};
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@ -89,12 +98,154 @@ IRQ_TYPE_EDGE_RISING)>,
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IRQ_TYPE_EDGE_RISING)>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&A57_0>,
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<&A57_1>,
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<&A57_2>,
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<&A57_3>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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iprocmed: iprocmed {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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iprocslow: iprocslow {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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smmu: mmu@64000000 {
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compatible = "arm,mmu-500";
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reg = <0x64000000 0x40000>;
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#global-interrupts = <2>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
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mmu-masters;
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};
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lcpll_ddr: lcpll_ddr@6501d058 {
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#clock-cells = <1>;
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compatible = "brcm,ns2-lcpll-ddr";
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reg = <0x6501d058 0x20>,
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<0x6501c020 0x4>,
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<0x6501d04c 0x4>;
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clocks = <&osc>;
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clock-output-names = "lcpll_ddr", "pcie_sata_usb",
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"ddr", "ddr_ch2_unused",
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"ddr_ch3_unused", "ddr_ch4_unused",
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"ddr_ch5_unused";
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};
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lcpll_ports: lcpll_ports@6501d078 {
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#clock-cells = <1>;
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compatible = "brcm,ns2-lcpll-ports";
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reg = <0x6501d078 0x20>,
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<0x6501c020 0x4>,
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<0x6501d054 0x4>;
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clocks = <&osc>;
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clock-output-names = "lcpll_ports", "wan", "rgmii",
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"ports_ch2_unused",
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"ports_ch3_unused",
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"ports_ch4_unused",
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"ports_ch5_unused";
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};
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genpll_scr: genpll_scr@6501d098 {
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#clock-cells = <1>;
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compatible = "brcm,ns2-genpll-scr";
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reg = <0x6501d098 0x32>,
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<0x6501c020 0x4>,
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<0x6501d044 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll_scr", "scr", "fs",
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"audio_ref", "scr_ch3_unused",
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"scr_ch4_unused", "scr_ch5_unused";
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};
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genpll_sw: genpll_sw@6501d0c4 {
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#clock-cells = <1>;
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compatible = "brcm,ns2-genpll-sw";
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reg = <0x6501d0c4 0x32>,
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<0x6501c020 0x4>,
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<0x6501d044 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll_sw", "rpe", "250", "nic",
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"chimp", "port", "sdio";
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};
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crmu: crmu@65024000 {
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compatible = "syscon";
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reg = <0x65024000 0x100>;
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};
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reboot@65024000 {
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compatible ="syscon-reboot";
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regmap = <&crmu>;
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offset = <0x90>;
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mask = <0xfffffffd>;
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};
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gic: interrupt-controller@65210000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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@ -105,14 +256,53 @@ gic: interrupt-controller@65210000 {
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<0x65260000 0x1000>;
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};
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i2c0: i2c@66080000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x66080000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@660b0000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x660b0000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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uart3: serial@66130000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x66130000 0x100>;
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interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <23961600>;
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clocks = <&osc>;
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status = "disabled";
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};
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hwrng: hwrng@66220000 {
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compatible = "brcm,iproc-rng200";
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reg = <0x66220000 0x28>;
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};
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nand: nand@66460000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
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reg = <0x66460000 0x600>,
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<0x67015408 0x600>,
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<0x66460f00 0x20>;
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reg-names = "nand", "iproc-idm", "iproc-ext";
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interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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brcm,nand-has-wp;
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};
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};
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};
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