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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
To support other register layouts in the future, add register pointers
of {control,status,reset,reset_clear}_regs into struct cpg_mssr_priv.
After that, we can remove unused macros like MSTPSR(). No behavioral
changes.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599810232-29035-3-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Yoshihiro Shimoda
Geert Uytterhoeven
parent
ffbf9cf3f9
commit
8b652aa8a1
@ -57,9 +57,6 @@ static const u16 mstpsr[] = {
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0x9A0, 0x9A4, 0x9A8, 0x9AC,
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};
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#define MSTPSR(i) mstpsr[i]
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/*
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* System Module Stop Control Register offsets
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*/
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@ -69,8 +66,6 @@ static const u16 smstpcr[] = {
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0x990, 0x994, 0x998, 0x99C,
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};
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#define SMSTPCR(i) smstpcr[i]
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/*
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* Standby Control Register offsets (RZ/A)
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* Base address is FRQCR register
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@ -81,8 +76,6 @@ static const u16 stbcr[] = {
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0x424, 0x428, 0x42C,
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};
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#define STBCR(i) stbcr[i]
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/*
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* Software Reset Register offsets
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*/
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@ -92,9 +85,6 @@ static const u16 srcr[] = {
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0x920, 0x924, 0x928, 0x92C,
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};
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#define SRCR(i) srcr[i]
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/* Realtime Module Stop Control Register offsets */
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#define RMSTPCR(i) (smstpcr[i] - 0x20)
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@ -102,8 +92,11 @@ static const u16 srcr[] = {
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#define MMSTPCR(i) (smstpcr[i] + 0x20)
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/* Software Reset Clearing Register offsets */
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#define SRSTCLR(i) (0x940 + (i) * 4)
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static const u16 srstclr[] = {
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0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
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0x960, 0x964, 0x968, 0x96C,
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};
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/**
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* Clock Pulse Generator / Module Standby and Software Reset Private Data
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@ -118,6 +111,10 @@ static const u16 srcr[] = {
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* @num_mod_clks: Number of Module Clocks in clks[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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* @notifiers: Notifier chain to save/restore clock state for system resume
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* @status_regs: Pointer to status registers array
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* @control_regs: Pointer to control registers array
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* @reset_regs: Pointer to reset registers array
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* @reset_clear_regs: Pointer to reset clearing registers array
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* @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
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* @smstpcr_saved[].val: Saved values of SMSTPCR[]
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* @clks: Array containing all Core and Module Clocks
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@ -137,6 +134,10 @@ struct cpg_mssr_priv {
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unsigned int last_dt_core_clk;
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struct raw_notifier_head notifiers;
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const u16 *status_regs;
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const u16 *control_regs;
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const u16 *reset_regs;
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const u16 *reset_clear_regs;
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struct {
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u32 mask;
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u32 val;
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@ -178,23 +179,23 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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spin_lock_irqsave(&priv->rmw_lock, flags);
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if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
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value = readb(priv->base + STBCR(reg));
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value = readb(priv->base + priv->control_regs[reg]);
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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writeb(value, priv->base + STBCR(reg));
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writeb(value, priv->base + priv->control_regs[reg]);
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/* dummy read to ensure write has completed */
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readb(priv->base + STBCR(reg));
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barrier_data(priv->base + STBCR(reg));
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readb(priv->base + priv->control_regs[reg]);
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barrier_data(priv->base + priv->control_regs[reg]);
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} else {
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value = readl(priv->base + SMSTPCR(reg));
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value = readl(priv->base + priv->control_regs[reg]);
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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writel(value, priv->base + SMSTPCR(reg));
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writel(value, priv->base + priv->control_regs[reg]);
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}
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spin_unlock_irqrestore(&priv->rmw_lock, flags);
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@ -203,14 +204,14 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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return 0;
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for (i = 1000; i > 0; --i) {
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if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
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if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
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break;
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cpu_relax();
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}
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if (!i) {
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dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
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priv->base + SMSTPCR(reg), bit);
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priv->base + priv->control_regs[reg], bit);
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return -ETIMEDOUT;
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}
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@ -234,9 +235,9 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
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u32 value;
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if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
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value = readb(priv->base + STBCR(clock->index / 32));
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value = readb(priv->base + priv->control_regs[clock->index / 32]);
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else
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value = readl(priv->base + MSTPSR(clock->index / 32));
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value = readl(priv->base + priv->status_regs[clock->index / 32]);
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return !(value & BIT(clock->index % 32));
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}
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@ -578,13 +579,13 @@ static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
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dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
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/* Reset module */
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writel(bitmask, priv->base + SRCR(reg));
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writel(bitmask, priv->base + priv->reset_regs[reg]);
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/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
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udelay(35);
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/* Release module from reset state */
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writel(bitmask, priv->base + SRSTCLR(reg));
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writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
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return 0;
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}
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@ -598,7 +599,7 @@ static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
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dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
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writel(bitmask, priv->base + SRCR(reg));
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writel(bitmask, priv->base + priv->reset_regs[reg]);
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return 0;
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}
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@ -612,7 +613,7 @@ static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
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dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
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writel(bitmask, priv->base + SRSTCLR(reg));
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writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
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return 0;
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}
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@ -624,7 +625,7 @@ static int cpg_mssr_status(struct reset_controller_dev *rcdev,
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unsigned int bit = id % 32;
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u32 bitmask = BIT(bit);
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return !!(readl(priv->base + SRCR(reg)) & bitmask);
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return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
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}
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static const struct reset_control_ops cpg_mssr_reset_ops = {
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@ -827,8 +828,8 @@ static int cpg_mssr_suspend_noirq(struct device *dev)
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if (priv->smstpcr_saved[reg].mask)
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priv->smstpcr_saved[reg].val =
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priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
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readb(priv->base + STBCR(reg)) :
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readl(priv->base + SMSTPCR(reg));
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readb(priv->base + priv->control_regs[reg]) :
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readl(priv->base + priv->control_regs[reg]);
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}
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/* Save core clocks */
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@ -857,22 +858,22 @@ static int cpg_mssr_resume_noirq(struct device *dev)
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continue;
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if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
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oldval = readb(priv->base + STBCR(reg));
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oldval = readb(priv->base + priv->control_regs[reg]);
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else
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oldval = readl(priv->base + SMSTPCR(reg));
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oldval = readl(priv->base + priv->control_regs[reg]);
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newval = oldval & ~mask;
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newval |= priv->smstpcr_saved[reg].val & mask;
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if (newval == oldval)
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continue;
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if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
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writeb(newval, priv->base + STBCR(reg));
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writeb(newval, priv->base + priv->control_regs[reg]);
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/* dummy read to ensure write has completed */
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readb(priv->base + STBCR(reg));
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barrier_data(priv->base + STBCR(reg));
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readb(priv->base + priv->control_regs[reg]);
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barrier_data(priv->base + priv->control_regs[reg]);
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continue;
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} else
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writel(newval, priv->base + SMSTPCR(reg));
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writel(newval, priv->base + priv->control_regs[reg]);
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/* Wait until enabled clocks are really enabled */
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mask &= ~priv->smstpcr_saved[reg].val;
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@ -880,7 +881,7 @@ static int cpg_mssr_resume_noirq(struct device *dev)
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continue;
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for (i = 1000; i > 0; --i) {
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oldval = readl(priv->base + MSTPSR(reg));
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oldval = readl(priv->base + priv->status_regs[reg]);
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if (!(oldval & mask))
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break;
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cpu_relax();
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@ -939,6 +940,17 @@ static int __init cpg_mssr_common_init(struct device *dev,
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priv->last_dt_core_clk = info->last_dt_core_clk;
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RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
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priv->reg_layout = info->reg_layout;
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if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
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priv->status_regs = mstpsr;
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priv->control_regs = smstpcr;
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priv->reset_regs = srcr;
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priv->reset_clear_regs = srstclr;
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} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
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priv->control_regs = stbcr;
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} else {
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error = -EINVAL;
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goto out_err;
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}
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for (i = 0; i < nclks; i++)
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priv->clks[i] = ERR_PTR(-ENOENT);
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