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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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iwlwifi: move D3_CFG_COMPLETE handling into DVM
The MVM firmware doesn't communicate this way, it instead assumes D3 configuration is complete after a specific host command (which must be last) has been sent. Handling this bit thus belongs into the firmware API code, i.e. DVM. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
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@ -426,6 +426,10 @@ static int iwlagn_mac_suspend(struct ieee80211_hw *hw,
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if (ret)
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goto error;
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/* let the ucode operate on its own */
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iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_SET,
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CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
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iwl_trans_d3_suspend(priv->trans);
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goto out;
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@ -509,6 +513,10 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
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goto out_unlock;
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}
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/* uCode is no longer operating by itself */
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iwl_write32(priv->trans, CSR_UCODE_DRV_GP1_CLR,
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CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
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base = priv->device_pointers.error_event_table;
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if (!iwlagn_hw_valid_rtc_data_addr(base)) {
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IWL_WARN(priv, "Invalid error table during resume!\n");
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@ -580,10 +580,6 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
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static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans)
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{
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/* let the ucode operate on its own */
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iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
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CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
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iwl_disable_interrupts(trans);
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iwl_pcie_disable_ict(trans);
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@ -643,9 +639,6 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
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return ret;
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}
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iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
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CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
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*status = IWL_D3_STATUS_ALIVE;
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return 0;
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}
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