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documentation: memory-barriers.txt: Correct example for reorderings

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Correct the example of memory orderings in memory-barriers.txt

Commit 615cc2c9cf "Documentation/memory-barriers.txt: fix important typo re
memory barriers" changed the assignment to x and y. Change the rest of the
example to match this change.

Reported-by: Ganesh Rapolu <ganesh.rapolu@hotmail.com>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
This commit is contained in:
Pranith Kumar 2014-09-02 23:34:29 -04:00 committed by Paul E. McKenney
parent 1f7870dd87
commit 8ab8b3e183
1 changed files with 11 additions and 11 deletions
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22
Documentation/memory-barriers.txt
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@ -121,22 +121,22 @@ For example, consider the following sequence of events:
The set of accesses as seen by the memory system in the middle can be arranged The set of accesses as seen by the memory system in the middle can be arranged
in 24 different combinations: in 24 different combinations:
STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
STORE B=4, ... STORE B=4, ...
... ...
and can thus result in four different combinations of values: and can thus result in four different combinations of values:
x == 1, y == 2 x == 2, y == 1
x == 1, y == 4 x == 2, y == 3
x == 3, y == 2 x == 4, y == 1
x == 3, y == 4 x == 4, y == 3
Furthermore, the stores committed by a CPU to the memory system may not be Furthermore, the stores committed by a CPU to the memory system may not be