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i.MX arm64 device tree update for 5.2:

Browse Source 
- Add initial i.MX8MM SoC and EVK board support.
  - Enable OPP table for cpufreq support on i.MX8MQ, i.MX8QXP and
    i.MX8MM.
  - A series from Andrey Smirnov to enable PCIe support for i.MX8MQ.
  - Add TMU (Thermal Management Unit) device on i.MX8MQ for managing
    thermal of CPU, GPU, and VPU.
  - Add SDMA and SAI2 devices for i.MX8MQ SoC and enable wm8524 audio
    support on EVK board.
  - Add LPUART, OCOTP and GPU devices for i.MX8MQ SoC.
  - Add initial i.MX8MQ based Zii Ultra board support
  - Add SCU general IRQ and watchdog support for i.MX8QXP.
  - Add audio related devices and PMU for LS1028A.
  - Enable SATA and cpuidle support for LX2160A.
  - Other small random updates.
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Merge tag 'imx-dt64-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree update for 5.2:
 - Add initial i.MX8MM SoC and EVK board support.
 - Enable OPP table for cpufreq support on i.MX8MQ, i.MX8QXP and
   i.MX8MM.
 - A series from Andrey Smirnov to enable PCIe support for i.MX8MQ.
 - Add TMU (Thermal Management Unit) device on i.MX8MQ for managing
   thermal of CPU, GPU, and VPU.
 - Add SDMA and SAI2 devices for i.MX8MQ SoC and enable wm8524 audio
   support on EVK board.
 - Add LPUART, OCOTP and GPU devices for i.MX8MQ SoC.
 - Add initial i.MX8MQ based Zii Ultra board support
 - Add SCU general IRQ and watchdog support for i.MX8QXP.
 - Add audio related devices and PMU for LS1028A.
 - Enable SATA and cpuidle support for LX2160A.
 - Other small random updates.

* tag 'imx-dt64-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (41 commits)
  arm64: dts: lx2160a: add cpu idle support
  arm64: dts: imx8mq: fix GPU clock frequency
  arm64: dts: fsl: imx8mq-evk: link regulator to GPU domain
  arm64: dts: imx8mm: Add cpufreq properties
  arm64: dts: imx8qxp-mek: Add i2c1 with pca9646
  arm64: dts: imx8qxp: enable scu general irq channel
  arm64: dts: imx8mq: add GPU node
  arm64: dts: imx: add Zii Ultra board support
  arm64: dts: imx8mq: fix higher CPU operating point
  arm64: dts: imx8mq-evk: Enable PCIE0 interface
  arm64: dts: imx8mq: Add nodes for PCIe IP blocks
  arm64: dts: imx8mq: Combine PCIE power domains
  arm64: dts: imx8mq: Add a node for SRC IP block
  arm64: dts: imx8mq: Mark iomuxc_gpr as i.MX6Q compatible
  arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes
  arm64: dts: lx2160a: add sata node support
  arm64: dts: ls1028a: Corrected the SATA ecc address
  arm64: dts: imx8mq: Change ahb clock for imx8mq
  arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string
  arm64: dts: imx8qxp: add system controller watchdog support
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-04-29 09:26:55 -07:00
commit 89f4f128ea
21 changed files with 2725 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm64/boot/dts/freescale/Makefile
View File

@ -20,5 +20,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb

4
arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts
View File

@ -87,6 +87,10 @@ &i2c1 {
status = "okay";
};
&pcie {
status = "okay";
};
&sai2 {
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -475,7 +475,7 @@ msi: msi-controller1@1572000 {
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
};
pcie@3400000 {
pcie: pcie@3400000 {
compatible = "fsl,ls1012a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */

62
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
View File

@ -32,6 +32,49 @@ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x00000000>;
};
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker Ext",
"Line", "Line In Jack";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Speaker Ext", "LINE_OUT";
simple-audio-card,cpu {
sound-dai = <&sai1>;
frame-master;
bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&sgtl5000>;
frame-master;
bitclock-master;
system-clock-frequency = <25000000>;
};
};
};
&duart0 {
@ -89,5 +132,24 @@ eeprom@57 {
reg = <0x57>;
};
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
sgtl5000: audio-codec@a {
#sound-dai-cells = <0>;
compatible = "fsl,sgtl5000";
reg = <0xa>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_1p8v>;
clocks = <&sys_mclk>;
};
};
};
};
&sai1 {
status = "okay";
};

63
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
View File

@ -28,6 +28,49 @@ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0000000>;
};
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker Ext",
"Line", "Line In Jack";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Speaker Ext", "LINE_OUT";
simple-audio-card,cpu {
sound-dai = <&sai4>;
frame-master;
bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&sgtl5000>;
frame-master;
bitclock-master;
system-clock-frequency = <25000000>;
};
};
};
&i2c0 {
@ -39,6 +82,22 @@ i2c-mux@77 {
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
sgtl5000: audio-codec@a {
#sound-dai-cells = <0>;
compatible = "fsl,sgtl5000";
reg = <0xa>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_1p8v>;
clocks = <&sys_mclk>;
sclk-strength = <3>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
@ -88,3 +147,7 @@ sgmii_phy0: ethernet-phy@2 {
&enetc_port1 {
status = "disabled";
};
&sai4 {
status = "okay";
};

64
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -89,6 +89,11 @@ IRQ_TYPE_LEVEL_LOW)>,
IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@6000000 {
compatible= "arm,gic-v3";
#address-cells = <2>;
@ -235,6 +240,21 @@ duart1: serial@21c0600 {
status = "disabled";
};
edma0: dma-controller@22c0000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x0 0x22c0000 0x0 0x10000>,
<0x0 0x22d0000 0x0 0x10000>,
<0x0 0x22e0000 0x0 0x10000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
clock-names = "dmamux0", "dmamux1";
clocks = <&clockgen 4 1>,
<&clockgen 4 1>;
};
gpio1: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
@ -277,7 +297,7 @@ wdog0: watchdog@23c0000 {
sata: sata@3200000 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
@ -336,6 +356,48 @@ smmu: iommu@5000000 {
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
};
sai1: audio-controller@f100000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0xf100000 0x0 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
<&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 4>,
<&edma0 1 3>;
status = "disabled";
};
sai2: audio-controller@f110000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0xf110000 0x0 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
<&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 6>,
<&edma0 1 5>;
status = "disabled";
};
sai4: audio-controller@f130000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0xf130000 0x0 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>,
<&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 10>,
<&edma0 1 9>;
status = "disabled";
};
pcie@1f0000000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
reg = <0x01 0xf0000000 0x0 0x100000>;

1
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
View File

@ -15,7 +15,6 @@ / {
model = "LS1043A RDB Board";
aliases {
crypto = &crypto;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;

2
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -18,6 +18,7 @@ / {
#size-cells = <2>;
aliases {
crypto = &crypto;
fman0 = &fman0;
ethernet0 = &enet0;
ethernet1 = &enet1;
@ -296,7 +297,6 @@ qspi: spi@1550000 {
interrupts = <0 99 0x4>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 0>, <&clockgen 4 0>;
big-endian;
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -215,8 +215,6 @@ qspi: spi@1550000 {
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
big-endian;
fsl,qspi-has-second-chip;
status = "disabled";
};

16
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
View File

@ -95,6 +95,22 @@ rtc@51 {
};
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&sata2 {
status = "okay";
};
&sata3 {
status = "okay";
};
&uart0 {
status = "okay";
};

16
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
View File

@ -128,6 +128,22 @@ rtc@51 {
};
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&sata2 {
status = "okay";
};
&sata3 {
status = "okay";
};
&uart0 {
status = "okay";
};

69
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -33,6 +33,7 @@ cpu@0 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@1 {
@ -48,6 +49,7 @@ cpu@1 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@100 {
@ -63,6 +65,7 @@ cpu@100 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@101 {
@ -78,6 +81,7 @@ cpu@101 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@200 {
@ -93,6 +97,7 @@ cpu@200 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@201 {
@ -108,6 +113,7 @@ cpu@201 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@300 {
@ -123,6 +129,7 @@ cpu@300 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@301 {
@ -138,6 +145,7 @@ cpu@301 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@400 {
@ -153,6 +161,7 @@ cpu@400 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@401 {
@ -168,6 +177,7 @@ cpu@401 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@500 {
@ -183,6 +193,7 @@ cpu@500 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@501 {
@ -198,6 +209,7 @@ cpu@501 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@600 {
@ -213,6 +225,7 @@ cpu@600 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@601 {
@ -228,6 +241,7 @@ cpu@601 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@700 {
@ -243,6 +257,7 @@ cpu@700 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cpu@701 {
@ -258,6 +273,7 @@ cpu@701 {
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw20>;
};
cluster0_l2: l2-cache0 {
@ -323,6 +339,15 @@ cluster7_l2: l2-cache7 {
cache-sets = <1024>;
cache-level = <2>;
};
cpu_pw20: cpu-pw20 {
compatible = "arm,idle-state";
idle-state-name = "PW20";
arm,psci-suspend-param = <0x0>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <6000>;
};
};
gic: interrupt-controller@6000000 {
@ -687,6 +712,50 @@ usb1: usb@3110000 {
status = "disabled";
};
sata0: sata@3200000 {
compatible = "fsl,lx2160a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
dma-coherent;
status = "disabled";
};
sata1: sata@3210000 {
compatible = "fsl,lx2160a-ahci";
reg = <0x0 0x3210000 0x0 0x10000>,
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
dma-coherent;
status = "disabled";
};
sata2: sata@3220000 {
compatible = "fsl,lx2160a-ahci";
reg = <0x0 0x3220000 0x0 0x10000>,
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
dma-coherent;
status = "disabled";
};
sata3: sata@3230000 {
compatible = "fsl,lx2160a-ahci";
reg = <0x0 0x3230000 0x0 0x10000>,
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
dma-coherent;
status = "disabled";
};
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;

235
arch/arm64/boot/dts/freescale/imx8mm-evk.dts Normal file
View File

@ -0,0 +1,235 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
/dts-v1/;
#include "imx8mm.dtsi"
/ {
model = "FSL i.MX8MM EVK board";
compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
status {
label = "status";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,led-act-blind-workaround;
at803x,eee-okay;
at803x,vddio-1p8v;
};
};
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8mm-pinfunc.h"
/ {
compatible = "fsl,imx8mm";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &fec1;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MM_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
};
A53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MM_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
};
A53_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MM_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
};
A53_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MM_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
};
A53_L2: l2-cache0 {
compatible = "cache";
};
};
a53_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <850000>;
clock-latency-ns = <150000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
};
osc_24m: clock-osc-24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc_24m";
};
clk_ext1: clock-ext1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext1";
};
clk_ext2: clock-ext2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext2";
};
clk_ext3: clock-ext3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext3";
};
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-output-names = "clk_ext4";
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
<0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@30200000 {
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@30210000 {
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x30210000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@30220000 {
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x30220000 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@30230000 {
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x30230000 0x10000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@30240000 {
compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
reg = <0x30240000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
status = "disabled";
};
wdog2: watchdog@30290000 {
compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
reg = <0x30290000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
status = "disabled";
};
wdog3: watchdog@302a0000 {
compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
reg = <0x302a0000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
status = "disabled";
};
sdma2: dma-controller@302c0000 {
compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
reg = <0x302c0000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
<&clk IMX8MM_CLK_SDMA2_ROOT>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
sdma3: dma-controller@302b0000 {
compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
reg = <0x302b0000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
<&clk IMX8MM_CLK_SDMA3_ROOT>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mm-iomuxc";
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
ocotp: ocotp-ctrl@30350000 {
compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
/* For nvmem subnodes */
#address-cells = <1>;
#size-cells = <1>;
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
reg = <0x30360000 0x10000>;
};
snvs: snvs@30370000 {
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
reg = <0x30370000 0x10000>;
snvs_rtc: snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
};
snvs_pwrkey: snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
};
};
clk: clock-controller@30380000 {
compatible = "fsl,imx8mm-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
};
src: reset-controller@30390000 {
compatible = "fsl,imx8mm-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
};
aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pwm1: pwm@30660000 {
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x30660000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
<&clk IMX8MM_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@30670000 {
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x30670000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
<&clk IMX8MM_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@30680000 {
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x30680000 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
<&clk IMX8MM_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@30690000 {
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x30690000 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
<&clk IMX8MM_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
};
aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ecspi1: spi@30820000 {
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
<&clk IMX8MM_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi2: spi@30830000 {
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
<&clk IMX8MM_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
<&clk IMX8MM_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
<&clk IMX8MM_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
<&clk IMX8MM_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
<&clk IMX8MM_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a20000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
status = "disabled";
};
i2c2: i2c@30a30000 {
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a30000 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
status = "disabled";
};
i2c3: i2c@30a40000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
reg = <0x30a40000 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
status = "disabled";
};
i2c4: i2c@30a50000 {
compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a50000 0x10000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
status = "disabled";
};
uart4: serial@30a60000 {
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
reg = <0x30a60000 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
<&clk IMX8MM_CLK_UART4_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
<&clk IMX8MM_CLK_SDMA1_ROOT>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
fec1: ethernet@30be0000 {
compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
<&clk IMX8MM_CLK_ENET1_ROOT>,
<&clk IMX8MM_CLK_ENET_TIMER>,
<&clk IMX8MM_CLK_ENET_REF>,
<&clk IMX8MM_CLK_ENET_PHY_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
<&clk IMX8MM_CLK_ENET_TIMER>,
<&clk IMX8MM_CLK_ENET_REF>,
<&clk IMX8MM_CLK_ENET_TIMER>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
status = "disabled";
};
};
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
<&clk IMX8MM_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
<&clk IMX8MM_SYS_PLL1_100M>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled";
};
usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
};
usbmisc1: usbmisc@32e40200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
#index-cells = <1>;
reg = <0x32e40200 0x200>;
};
usbotg2: usb@32e50000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
reg = <0x32e50000 0x200>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
<&clk IMX8MM_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
<&clk IMX8MM_SYS_PLL1_100M>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
status = "disabled";
};
usbphynop2: usbphynop2 {
compatible = "usb-nop-xceiv";
clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
clock-names = "main_clk";
};
usbmisc2: usbmisc@32e50200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
#index-cells = <1>;
reg = <0x32e50200 0x200>;
};
};
dma_apbh: dma-controller@33000000 {
compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x33000000 0x2000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
};
gpmi: nand-controller@33002000{
compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bch";
clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
clock-names = "gpmi_io", "gpmi_bch_apb";
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
status = "disabled";
};
};
};

129
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -21,6 +21,12 @@ memory@40000000 {
reg = <0x00000000 0x40000000 0 0xc0000000>;
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
@ -31,6 +37,63 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 {
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
buck2_reg: regulator-buck2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_buck2>;
compatible = "regulator-gpio";
regulator-name = "vdd_arm";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
states = <1000000 0x0
900000 0x1>;
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
sound-wm8524 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&cpudai>;
simple-audio-card,bitclock-master = <&cpudai>;
simple-audio-card,widgets =
"Line", "Left Line Out Jack",
"Line", "Right Line Out Jack";
simple-audio-card,routing =
"Left Line Out Jack", "LINEVOUTL",
"Right Line Out Jack", "LINEVOUTR";
cpudai: simple-audio-card,cpu {
sound-dai = <&sai2>;
};
link_codec: simple-audio-card,codec {
sound-dai = <&wm8524>;
clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
};
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&fec1 {
@ -52,6 +115,26 @@ ethphy0: ethernet-phy@0 {
};
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_reset>;
wl-reg-on {
gpio-hog;
gpios = <29 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -143,6 +226,22 @@ vgen6_reg: vgen6 {
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@ -203,6 +302,13 @@ &wdog1 {
};
&iomuxc {
pinctrl_buck2: vddarmgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
@ -230,6 +336,13 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
@ -248,6 +361,16 @@ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
@ -347,4 +470,10 @@ pinctrl_wdog: wdog1grp {
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_wifi_reset: wifiresetgrp {
fsl,pins = <
MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
>;
};
};

95
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts Normal file
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@ -0,0 +1,95 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2019 Zodiac Inflight Innovations
*/
/dts-v1/;
#include "imx8mq-zii-ultra.dtsi"
/ {
model = "ZII i.MX8MQ Ultra RMB3 Board";
compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
nor_flash: flash@0 {
compatible = "st,n25q128a13", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&i2c2 {
temp-sense@48 {
compatible = "national,lm75";
reg = <0x48>;
};
};
&i2c4 {
touchscreen@20 {
compatible = "syna,rmi4-i2c";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ts>;
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
#address-cells = <1>;
#size-cells = <0>;
rmi4-f01@1 {
reg = <0x1>;
syna,nosleep-mode = <2>;
};
rmi4-f11@11 {
reg = <0x11>;
touchscreen-inverted-x;
touchscreen-swapped-x-y;
syna,sensor-type = <1>;
};
rmi4-f12@12 {
reg = <0x12>;
touchscreen-inverted-x;
touchscreen-swapped-x-y;
syna,sensor-type = <1>;
};
};
touchscreen@2a {
compatible = "eeti,exc3000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ts>;
reg = <0x2a>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
touchscreen-inverted-x;
touchscreen-swapped-x-y;
status = "disabled";
};
};
&usbhub {
swap-dx-lanes = <0>;
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
>;
};
};

24
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2019 Zodiac Inflight Innovations
*/
/dts-v1/;
#include "imx8mq-zii-ultra.dtsi"
/ {
model = "ZII i.MX8MQ Ultra Zest Board";
compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq";
};
&i2c4 {
touchscreen@4a {
compatible = "atmel,maxtouch";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ts>;
reg = <0x4a>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
};
};

725
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi Normal file
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@ -0,0 +1,725 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2019 Zodiac Inflight Innovations
*/
#include "imx8mq.dtsi"
/ {
aliases {
mdio-gpio0 = &mdio0;
rtc0 = &ds1341;
};
chosen {
stdout-path = &uart1;
};
mdio0: bitbang-mdio {
compatible = "virtual,mdio-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
};
};
pcie0_refclk: clock-pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie1_refclk: clock-pcie1-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_12p0_main: regulator-12p0-main {
compatible = "regulator-fixed";
regulator-name = "12V_MAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_5p0_main: regulator-5p0-main {
compatible = "regulator-fixed";
vin-supply = <&reg_12p0_main>;
regulator-name = "5V_MAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_3p3_main: regulator-3p3-main {
compatible = "regulator-fixed";
vin-supply = <&reg_12p0_main>;
regulator-name = "3V3V_MAIN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0_user_usb: regulator-5p0-user-usb {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_user_usb>;
vin-supply = <&reg_5p0_main>;
regulator-name = "5V_USER_USB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 12 GPIO_ACTIVE_LOW>;
startup-delay-us = <1000>;
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
compatible = "regulator-fixed";
vin-supply = <&reg_3p3_main>;
regulator-name = "3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_arm: regulator-arm {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_arm>;
compatible = "regulator-gpio";
vin-supply = <&reg_12p0_main>;
regulator-name = "0V9_ARM";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
states = <1000000 0x0
900000 0x1>;
regulator-always-on;
};
};
&A53_0 {
cpu-supply = <&reg_arm>;
};
&A53_1 {
cpu-supply = <&reg_arm>;
};
&A53_2 {
cpu-supply = <&reg_arm>;
};
&A53_3 {
cpu-supply = <&reg_arm>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-handle = <&phy0>;
phy-mode = "rmii";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
switch: switch@0 {
compatible = "marvell,mv88e6085";
pinctrl-0 = <&pinctrl_switch_irq>;
pinctrl-names = "default";
reg = <0>;
dsa,member = <0 0>;
eeprom-length = <512>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "gigabit_proc";
phy-handle = <&switchphy0>;
};
port@1 {
reg = <1>;
label = "netaux";
phy-handle = <&switchphy1>;
};
port@2 {
reg = <2>;
label = "cpu";
ethernet = <&fec1>;
fixed-link {
speed = <100>;
full-duplex;
};
};
port@3 {
reg = <3>;
label = "netright";
phy-handle = <&switchphy3>;
};
port@4 {
reg = <4>;
label = "netleft";
phy-handle = <&switchphy4>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switchphy0: switchphy@0 {
reg = <0>;
interrupt-parent = <&switch>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy1: switchphy@1 {
reg = <1>;
interrupt-parent = <&switch>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy2: switchphy@2 {
reg = <2>;
interrupt-parent = <&switch>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy3: switchphy@3 {
reg = <3>;
interrupt-parent = <&switch>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy4: switchphy@4 {
reg = <4>;
interrupt-parent = <&switch>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio3_hog>;
usb-emulation {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "usb-emulation";
};
usb-mode1 {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-mode1";
};
usb-mode2 {
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-mode2";
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <975000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1675000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1625000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3625000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
eeprom@54 {
compatible = "atmel,24c128";
reg = <0x54>;
};
ds1341: rtc@68 {
compatible = "dallas,ds1341";
reg = <0x68>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
usbhub: usbhub@2c {
compatible ="microchip,usb2513b";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhub>;
reg = <0x2c>;
reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
};
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
rave-sp {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
watchdog {
compatible = "zii,rave-sp-watchdog";
};
backlight {
compatible = "zii,rave-sp-backlight";
};
pwrbutton {
compatible = "zii,rave-sp-pwrbutton";
};
eeprom@a3 {
compatible = "zii,rave-sp-eeprom";
reg = <0xa3 0x4000>;
zii,eeprom-name = "dds-eeprom";
};
eeprom@a4 {
compatible = "zii,rave-sp-eeprom";
reg = <0xa4 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
zii,eeprom-name = "main-eeprom";
};
};
};
&usb3_phy0 {
vbus-supply = <&reg_5p0_user_usb>;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_5p0_main>;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
&pgc_vpu {
power-supply = <&sw1c_reg>;
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&sw4_reg>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&snvs_rtc {
status = "disabled";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>;
};
pinctrl_fec1_phy_reset: fec1phyresetgrp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x11
>;
};
pinctrl_gpio3_hog: gpio3hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_mdio_bitbang: bitbangmdiogrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x44
MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x64
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x66
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x6
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x66
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x6
>;
};
pinctrl_reg_arm: regarmgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>;
};
pinctrl_reg_usdhc2: regusdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_reg_user_usb: reguserusbgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6
>;
};
pinctrl_switch_irq: switchgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
>;
};
pinctrl_ts: tsgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x96
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
>;
};
pinctrl_usbhub: usbhubgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
};

309
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -6,8 +6,10 @@
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8mq-pinfunc.h"
/ {
@ -87,32 +89,48 @@ A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
A53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
A53_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
A53_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
};
A53_L2: l2-cache0 {
@ -120,6 +138,24 @@ A53_L2: l2-cache0 {
};
};
a53_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <900000>;
clock-latency-ns = <150000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@ -132,6 +168,67 @@ psci {
method = "smc";
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 0>;
trips {
cpu_alert: cpu-alert {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu-crit {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 1>;
trips {
gpu-crit {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
};
vpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 2>;
trips {
vpu-crit {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
@ -160,6 +257,7 @@ gpio1: gpio@30200000 {
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -171,6 +269,7 @@ gpio2: gpio@30210000 {
reg = <0x30210000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -182,6 +281,7 @@ gpio3: gpio@30220000 {
reg = <0x30220000 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -193,6 +293,7 @@ gpio4: gpio@30230000 {
reg = <0x30230000 0x10000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -204,12 +305,65 @@ gpio5: gpio@30240000 {
reg = <0x30240000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
tmu: tmu@30260000 {
compatible = "fsl,imx8mq-tmu";
reg = <0x30260000 0x10000>;
interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
fsl,tmu-calibration = <0x00000000 0x00000023
0x00000001 0x00000029
0x00000002 0x0000002f
0x00000003 0x00000035
0x00000004 0x0000003d
0x00000005 0x00000043
0x00000006 0x0000004b
0x00000007 0x00000051
0x00000008 0x00000057
0x00000009 0x0000005f
0x0000000a 0x00000067
0x0000000b 0x0000006f
0x00010000 0x0000001b
0x00010001 0x00000023
0x00010002 0x0000002b
0x00010003 0x00000033
0x00010004 0x0000003b
0x00010005 0x00000043
0x00010006 0x0000004b
0x00010007 0x00000055
0x00010008 0x0000005d
0x00010009 0x00000067
0x0001000a 0x00000070
0x00020000 0x00000017
0x00020001 0x00000023
0x00020002 0x0000002d
0x00020003 0x00000037
0x00020004 0x00000041
0x00020005 0x0000004b
0x00020006 0x00000057
0x00020007 0x00000063
0x00020008 0x0000006f
0x00030000 0x00000015
0x00030001 0x00000021
0x00030002 0x0000002d
0x00030003 0x00000039
0x00030004 0x00000045
0x00030005 0x00000053
0x00030006 0x0000005f
0x00030007 0x00000071>;
#thermal-sensor-cells = <1>;
};
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
@ -234,16 +388,35 @@ wdog3: watchdog@302a0000 {
status = "disabled";
};
sdma2: sdma@302c0000 {
compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
reg = <0x302c0000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
<&clk IMX8MQ_CLK_SDMA2_ROOT>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx8mq-iomuxc";
reg = <0x30330000 0x10000>;
};
iomuxc_gpr: syscon@30340000 {
compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
ocotp: ocotp-ctrl@30350000 {
compatible = "fsl,imx8mq-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
#address-cells = <1>;
#size-cells = <1>;
};
anatop: syscon@30360000 {
compatible = "fsl,imx8mq-anatop", "syscon";
reg = <0x30360000 0x10000>;
@ -278,6 +451,12 @@ clk: clock-controller@30380000 {
"clk_ext3", "clk_ext4";
};
src: reset-controller@30390000 {
compatible = "fsl,imx8mq-src", "syscon";
reg = <0x30390000 0x10000>;
#reset-cells = <1>;
};
gpc: gpc@303a0000 {
compatible = "fsl,imx8mq-gpc";
reg = <0x303a0000 0x10000>;
@ -294,9 +473,25 @@ pgc_mipi: power-domain@0 {
reg = <IMX8M_POWER_DOMAIN_MIPI>;
};
pgc_pcie1: power-domain@1 {
/*
* As per comment in ATF source code:
*
* PCIE1 and PCIE2 share the
* same reset signal, if we
* power down PCIE2, PCIE1
* will be held in reset too.
*
* So instead of creating two
* separate power domains for
* PCIE1 and PCIE2 we create a
* link between both and use
* it as a shared PCIE power
* domain.
*/
pgc_pcie: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8M_POWER_DOMAIN_PCIE1>;
power-domains = <&pgc_pcie2>;
};
pgc_otg1: power-domain@2 {
@ -478,6 +673,21 @@ uart2: serial@30890000 {
status = "disabled";
};
sai2: sai@308b0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx8mq-sai",
"fsl,imx6sx-sai";
reg = <0x308b0000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
<&clk IMX8MQ_CLK_SAI2_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
reg = <0x30a20000 0x10000>;
@ -575,6 +785,17 @@ qspi0: spi@30bb0000 {
status = "disabled";
};
sdma1: sdma@30bd0000 {
compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
<&clk IMX8MQ_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
fec1: ethernet@30be0000 {
compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
@ -594,6 +815,30 @@ fec1: ethernet@30be0000 {
};
};
gpu: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x40000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
<&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
<&clk IMX8MQ_CLK_GPU_AXI>,
<&clk IMX8MQ_CLK_GPU_AHB>;
clock-names = "core", "shader", "bus", "reg";
assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
<&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
<&clk IMX8MQ_CLK_GPU_AXI>,
<&clk IMX8MQ_CLK_GPU_AHB>,
<&clk IMX8MQ_GPU_PLL_BYPASS>;
assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_GPU_PLL>;
assigned-clock-rates = <800000000>, <800000000>,
<800000000>, <800000000>, <0>;
power-domains = <&pgc_gpu>;
};
usb_dwc3_0: usb@38100000 {
compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
reg = <0x38100000 0x10000>;
@ -658,6 +903,66 @@ usb3_phy1: usb-phy@382f0040 {
status = "disabled";
};
pcie0: pcie@33800000 {
compatible = "fsl,imx8mq-pcie";
reg = <0x33800000 0x400000>,
<0x1ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
status = "disabled";
};
pcie1: pcie@33c00000 {
compatible = "fsl,imx8mq-pcie";
reg = <0x33c00000 0x400000>,
<0x27f00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY2>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
status = "disabled";
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */

95
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -60,6 +60,82 @@ ethphy1: ethernet-phy@1 {
};
};
&adma_i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9646", "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
pressure-sensor@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
pca9557_a: gpio@1a {
compatible = "nxp,pca9557";
reg = <0x1a>;
gpio-controller;
#gpio-cells = <2>;
};
pca9557_b: gpio@1d {
compatible = "nxp,pca9557";
reg = <0x1d>;
gpio-controller;
#gpio-cells = <2>;
};
light-sensor@44 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isl29023>;
compatible = "isil,isl29023";
reg = <0x44>;
interrupt-parent = <&lsio_gpio1>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
};
};
};
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@ -100,6 +176,25 @@ IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_ioexp_rst: ioexp_rst_grp {
fsl,pins = <
IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
>;
};
pinctrl_isl29023: isl29023grp {
fsl,pins = <
IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020

89
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@ -21,6 +21,7 @@ aliases {
mmc1 = &usdhc2;
mmc2 = &usdhc3;
serial0 = &adma_lpuart0;
mu1 = &lsio_mu1;
};
cpus {
@ -34,6 +35,9 @@ A35_0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_1: cpu@1 {
@ -42,6 +46,9 @@ A35_1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_2: cpu@2 {
@ -50,6 +57,9 @@ A35_2: cpu@2 {
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_3: cpu@3 {
@ -58,6 +68,9 @@ A35_3: cpu@3 {
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
A35_L2: l2-cache0 {
@ -65,6 +78,24 @@ A35_L2: l2-cache0 {
};
};
a35_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
@ -87,7 +118,8 @@ psci {
scu {
compatible = "fsl,imx-scu";
mbox-names = "tx0", "tx1", "tx2", "tx3",
"rx0", "rx1", "rx2", "rx3";
"rx0", "rx1", "rx2", "rx3",
"gip3";
mboxes = <&lsio_mu1 0 0
&lsio_mu1 0 1
&lsio_mu1 0 2
@ -95,7 +127,8 @@ &lsio_mu1 0 3
&lsio_mu1 1 0
&lsio_mu1 1 1
&lsio_mu1 1 2
&lsio_mu1 1 3>;
&lsio_mu1 1 3
&lsio_mu1 3 3>;
clk: clock-controller {
compatible = "fsl,imx8qxp-clk";
@ -163,6 +196,39 @@ adma_lpuart0: serial@5a060000 {
status = "disabled";
};
adma_lpuart1: serial@5a070000 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_UART_1>;
status = "disabled";
};
adma_lpuart2: serial@5a080000 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_UART_2>;
status = "disabled";
};
adma_lpuart3: serial@5a090000 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_UART_3>;
status = "disabled";
};
adma_i2c0: i2c@5a800000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a800000 0x4000>;
@ -328,7 +394,7 @@ lsio_mu0: mailbox@5d1b0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <0>;
#mbox-cells = <2>;
status = "disabled";
};
@ -339,11 +405,19 @@ lsio_mu1: mailbox@5d1c0000 {
#mbox-cells = <2>;
};
lsio_mu2: mailbox@5d1d0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1d0000 0x10000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
lsio_mu3: mailbox@5d1e0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1e0000 0x10000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <0>;
#mbox-cells = <2>;
status = "disabled";
};
@ -351,7 +425,7 @@ lsio_mu4: mailbox@5d1f0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1f0000 0x10000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <0>;
#mbox-cells = <2>;
status = "disabled";
};
@ -443,4 +517,9 @@ lsio_gpio7: gpio@5d0f0000 {
power-domains = <&pd IMX_SC_R_GPIO_7>;
};
};
watchdog {
compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
timeout-sec = <60>;
};
};