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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 17:36:50 +07:00
bnx2x: Function Level Reset Final Cleanup
1. Fix bug where return value is ignored 2. Improve printouts 3. Fix typos Signed-off-by: Ariel Elior <ariele@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1017,8 +1017,8 @@ void bnx2x_panic_dump(struct bnx2x *bp)
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* initialization.
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* initialization.
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*/
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*/
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#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
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#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
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#define FLR_WAIT_INTERAVAL 50 /* usec */
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#define FLR_WAIT_INTERVAL 50 /* usec */
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#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
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#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
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struct pbf_pN_buf_regs {
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struct pbf_pN_buf_regs {
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int pN;
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int pN;
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@ -1051,7 +1051,7 @@ static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
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while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
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while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
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(init_crd - crd_start))) {
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(init_crd - crd_start))) {
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if (cur_cnt--) {
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if (cur_cnt--) {
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udelay(FLR_WAIT_INTERAVAL);
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udelay(FLR_WAIT_INTERVAL);
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crd = REG_RD(bp, regs->crd);
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crd = REG_RD(bp, regs->crd);
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crd_freed = REG_RD(bp, regs->crd_freed);
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crd_freed = REG_RD(bp, regs->crd_freed);
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} else {
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} else {
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@ -1065,7 +1065,7 @@ static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
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}
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}
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}
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}
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DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
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DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
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poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
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poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
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}
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}
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static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
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static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
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@ -1083,7 +1083,7 @@ static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
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while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
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while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
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if (cur_cnt--) {
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if (cur_cnt--) {
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udelay(FLR_WAIT_INTERAVAL);
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udelay(FLR_WAIT_INTERVAL);
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occup = REG_RD(bp, regs->lines_occup);
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occup = REG_RD(bp, regs->lines_occup);
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freed = REG_RD(bp, regs->lines_freed);
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freed = REG_RD(bp, regs->lines_freed);
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} else {
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} else {
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@ -1097,7 +1097,7 @@ static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
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}
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}
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}
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}
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DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
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DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
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poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
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poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
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}
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}
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static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
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static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
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@ -1107,7 +1107,7 @@ static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
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u32 val;
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u32 val;
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while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
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while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
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udelay(FLR_WAIT_INTERAVAL);
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udelay(FLR_WAIT_INTERVAL);
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return val;
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return val;
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}
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}
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@ -1220,7 +1220,7 @@ static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
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int ret = 0;
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int ret = 0;
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if (REG_RD(bp, comp_addr)) {
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if (REG_RD(bp, comp_addr)) {
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BNX2X_ERR("Cleanup complete is not 0\n");
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BNX2X_ERR("Cleanup complete was not 0 before sending\n");
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return 1;
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return 1;
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}
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}
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@ -1229,7 +1229,7 @@ static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
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op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
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op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
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op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
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op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
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DP(BNX2X_MSG_SP, "FW Final cleanup\n");
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DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
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REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
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REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
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if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
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if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
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@ -1344,6 +1344,7 @@ static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
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REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
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REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
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/* Poll HW usage counters */
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/* Poll HW usage counters */
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DP(BNX2X_MSG_SP, "Polling usage counters\n");
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if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
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if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
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return -EBUSY;
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return -EBUSY;
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@ -6697,13 +6698,16 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
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u16 cdu_ilt_start;
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u16 cdu_ilt_start;
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u32 addr, val;
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u32 addr, val;
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u32 main_mem_base, main_mem_size, main_mem_prty_clr;
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u32 main_mem_base, main_mem_size, main_mem_prty_clr;
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int i, main_mem_width;
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int i, main_mem_width, rc;
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DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
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DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
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/* FLR cleanup - hmmm */
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/* FLR cleanup - hmmm */
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if (!CHIP_IS_E1x(bp))
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if (!CHIP_IS_E1x(bp)) {
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bnx2x_pf_flr_clnup(bp);
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rc = bnx2x_pf_flr_clnup(bp);
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if (rc)
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return rc;
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}
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/* set MSI reconfigure capability */
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/* set MSI reconfigure capability */
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if (bp->common.int_block == INT_BLOCK_HC) {
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if (bp->common.int_block == INT_BLOCK_HC) {
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