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drm/amd/display: update p-state latency for renoir when using lpddr4
[Why] DF team has produced more optimized latency numbers, for lpddr4 [How] change the p-state laency in the lpddr4 wm table to the new latency number Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2853ecc661
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@ -562,7 +562,7 @@ struct wm_table lpddr4_wm_table = {
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{
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{
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.wm_inst = WM_A,
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.wm_inst = WM_A,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 23.84,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 12.5,
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.sr_exit_time_us = 12.5,
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.sr_enter_plus_exit_time_us = 17.0,
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.sr_enter_plus_exit_time_us = 17.0,
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.valid = true,
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.valid = true,
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@ -570,7 +570,7 @@ struct wm_table lpddr4_wm_table = {
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{
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{
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.wm_inst = WM_B,
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.wm_inst = WM_B,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 23.84,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 12.5,
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.sr_exit_time_us = 12.5,
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.sr_enter_plus_exit_time_us = 17.0,
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.sr_enter_plus_exit_time_us = 17.0,
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.valid = true,
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.valid = true,
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@ -578,7 +578,7 @@ struct wm_table lpddr4_wm_table = {
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{
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{
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.wm_inst = WM_C,
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.wm_inst = WM_C,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 23.84,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 12.5,
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.sr_exit_time_us = 12.5,
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.sr_enter_plus_exit_time_us = 17.0,
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.sr_enter_plus_exit_time_us = 17.0,
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.valid = true,
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.valid = true,
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@ -586,7 +586,7 @@ struct wm_table lpddr4_wm_table = {
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{
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{
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.wm_inst = WM_D,
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.wm_inst = WM_D,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 23.84,
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.pstate_latency_us = 11.65333,
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.sr_exit_time_us = 12.5,
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.sr_exit_time_us = 12.5,
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.sr_enter_plus_exit_time_us = 17.0,
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.sr_enter_plus_exit_time_us = 17.0,
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.valid = true,
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.valid = true,
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