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drm/i915: Enable/disable the dithering for LVDS based on VBT setting
Enable/disable the dithering for LVDS based on VBT setting. On the 965/g4x platform the dithering flag is defined in LVDS register. And on the ironlake the dithering flag is defined in pipeconf register. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
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@ -975,6 +975,8 @@
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#define LVDS_PORT_EN (1 << 31)
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/* Selects pipe B for LVDS data. Must be set on pre-965. */
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#define LVDS_PIPEB_SELECT (1 << 30)
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/* LVDS dithering flag on 965/g4x platform */
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#define LVDS_ENABLE_DITHER (1 << 25)
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/* Enable border for unscaled (or aspect-scaled) display */
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#define LVDS_BORDER_ENABLE (1 << 15)
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/*
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@ -1744,6 +1746,8 @@
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/* Display & cursor control */
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/* dithering flag on Ironlake */
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#define PIPE_ENABLE_DITHER (1 << 4)
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/* Pipe A */
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#define PIPEADSL 0x70000
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#define PIPEACONF 0x70008
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@ -3195,7 +3195,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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* appropriately here, but we need to look more thoroughly into how
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* panels behave in the two modes.
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*/
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/* set the dithering flag */
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if (IS_I965G(dev)) {
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if (dev_priv->lvds_dither) {
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if (IS_IRONLAKE(dev))
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pipeconf |= PIPE_ENABLE_DITHER;
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else
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lvds |= LVDS_ENABLE_DITHER;
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} else {
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if (IS_IRONLAKE(dev))
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pipeconf &= ~PIPE_ENABLE_DITHER;
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else
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lvds &= ~LVDS_ENABLE_DITHER;
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}
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}
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I915_WRITE(lvds_reg, lvds);
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I915_READ(lvds_reg);
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}
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