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drm/i915/glk: Fix degamma lut programming

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Fixed the glk degamma lut programming which currently
was hard coding a linear lut all the time, making degamma
block of glk basically a pass through.

Currently degamma lut for glk is assigned as 0 in platform
configuration. Updated the same to 33 as per the hardware
capability. IGT tests for degamma were getting skipped due to
this, spotted by Swati.

ToDo: The current gamma/degamm lut ABI has just 16bit for each
color component. This is not enough for GLK+, since input
precision is increased to 3.16 which will need 19bit entries.

v2: Added Matt's RB.

v3: Changed uint32_t to u32.

v4: Fixed Maarten's review comment

Credits-to: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1549893025-21837-2-git-send-email-uma.shankar@intel.com
This commit is contained in:
Uma Shankar 2019-02-11 19:20:21 +05:30 committed by Maarten Lankhorst
parent b3b0391af2
commit 8957129cb3
2 changed files with 35 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/i915_pci.c
View File

@ -73,7 +73,7 @@
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
} }
#define GLK_COLORS \ #define GLK_COLORS \
.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024, \ .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
DRM_COLOR_LUT_EQUAL_CHANNELS, \ DRM_COLOR_LUT_EQUAL_CHANNELS, \
} }

52
drivers/gpu/drm/i915/intel_color.c
View File

@ -489,6 +489,12 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1); I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1); I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
} }
/*
* Reset the index, otherwise it prevents the legacy palette to be
* written properly.
*/
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
} }
/* Loads the palette/gamma unit for the CRTC on Broadwell+. */ /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
@ -496,7 +502,6 @@ static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
{ {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (crtc_state_is_legacy_gamma(crtc_state)) { if (crtc_state_is_legacy_gamma(crtc_state)) {
i9xx_load_luts(crtc_state); i9xx_load_luts(crtc_state);
@ -504,12 +509,6 @@ static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
bdw_load_degamma_lut(crtc_state); bdw_load_degamma_lut(crtc_state);
bdw_load_gamma_lut(crtc_state, bdw_load_gamma_lut(crtc_state,
INTEL_INFO(dev_priv)->color.degamma_lut_size); INTEL_INFO(dev_priv)->color.degamma_lut_size);
/*
* Reset the index, otherwise it prevents the legacy palette to be
* written properly.
*/
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
} }
} }
@ -518,7 +517,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe; enum pipe pipe = crtc->pipe;
const u32 lut_size = 33; const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
u32 i; u32 i;
/* /*
@ -529,15 +528,33 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0); I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT); I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
if (crtc_state->base.degamma_lut) {
struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
for (i = 0; i < lut_size; i++) {
/* /*
* FIXME: The pipe degamma table in geminilake doesn't support * First 33 entries represent range from 0 to 1.0
* different values per channel, so this just loads a linear table. * 34th and 35th entry will represent extended range
* inputs 3.0 and 7.0 respectively, currently clamped
* at 1.0. Since the precision is 16bit, the user
* value can be directly filled to register.
* The pipe degamma table in GLK+ onwards doesn't
* support different values per channel, so this just
* programs green value which will be equal to Red and
* Blue into the lut registers.
* ToDo: Extend to max 7.0. Enable 32 bit input value
* as compared to just 16 to achieve this.
*/ */
I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
}
} else {
/* load a linear table. */
for (i = 0; i < lut_size; i++) { for (i = 0; i < lut_size; i++) {
u32 v = (i * (1 << 16)) / (lut_size - 1); u32 v = (i * (1 << 16)) / (lut_size - 1);
I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v); I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
} }
}
/* Clamp values > 1.0. */ /* Clamp values > 1.0. */
while (i++ < 35) while (i++ < 35)
@ -546,23 +563,12 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
static void glk_load_luts(const struct intel_crtc_state *crtc_state) static void glk_load_luts(const struct intel_crtc_state *crtc_state)
{ {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
glk_load_degamma_lut(crtc_state); glk_load_degamma_lut(crtc_state);
if (crtc_state_is_legacy_gamma(crtc_state)) { if (crtc_state_is_legacy_gamma(crtc_state))
i9xx_load_luts(crtc_state); i9xx_load_luts(crtc_state);
} else { else
bdw_load_gamma_lut(crtc_state, 0); bdw_load_gamma_lut(crtc_state, 0);
/*
* Reset the index, otherwise it prevents the legacy palette to be
* written properly.
*/
I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}
} }
static void cherryview_load_luts(const struct intel_crtc_state *crtc_state) static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)