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media: hevc: Fix dependent slice segment flags
[ Upstream commit 67a7e53d5b21f3a84efc03a4e62db7caf97841ef ] Dependent slice segment flag for PPS control is misnamed. It should have "enabled" at the end. It only tells if this flag is present in slice header or not and not the actual value. Fix this by renaming the PPS flag and introduce another flag for slice control which tells actual value. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -4030,7 +4030,7 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
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:stub-columns: 0
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:widths: 1 1 2
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* - ``V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT``
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* - ``V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED``
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- 0x00000001
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-
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* - ``V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT``
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@ -4238,6 +4238,9 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
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* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED``
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- 0x00000100
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-
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* - ``V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT``
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- 0x00000200
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-
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.. c:type:: v4l2_hevc_dpb_entry
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@ -477,8 +477,8 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
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slice_params->flags);
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reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT,
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V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT,
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pps->flags);
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V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT,
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slice_params->flags);
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/* FIXME: For multi-slice support. */
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reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC;
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@ -81,7 +81,7 @@ struct v4l2_ctrl_hevc_sps {
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__u64 flags;
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};
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#define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 0)
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#define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED (1ULL << 0)
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#define V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT (1ULL << 1)
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#define V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED (1ULL << 2)
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#define V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT (1ULL << 3)
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@ -160,6 +160,7 @@ struct v4l2_hevc_pred_weight_table {
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV (1ULL << 6)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 9)
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struct v4l2_ctrl_hevc_slice_params {
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__u32 bit_size;
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