mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 02:16:45 +07:00
MIPS changes for 4.15
These are the main MIPS changes for 4.15.
Fixes:
- ralink: Fix MT7620 PCI build issues (4.5)
- Disable cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN for 32-bit SMP
(4.1)
- Fix MIPS64 FP save/restore on 32-bit kernels (4.0)
- ptrace: Pick up ptrace/seccomp changed syscall numbers (3.19)
- ralink: Fix MT7628 pinmux (3.19)
- BCM47XX: Fix LED inversion on WRT54GSv1 (3.17)
- Fix n32 core dumping as o32 since regset support (3.13)
- ralink: Drop obsolete USB_ARCH_HAS_HCD select
Build system:
- Default to "generic" (multiplatform) system type instead of IP22
- Use generic little endian MIPS32 r2 configuration as default defconfig
instead of ip22_defconfig
FPU emulation:
- Fix exception generation for certain R6 FPU instructions
SMP:
- Allow __cpu_number_map to be larger than NR_CPUS for sparse CPU id
spaces
Miscellaneous:
- Add iomem resource for kernel bss section for kexec/kdump
- Atomics: Nudge writes on bit unlock
- DT files: Standardise "ok" -> "okay"
Platform support:
BMIPS:
- Enable HARDIRQS_SW_RESEND
Broadcom BCM63XX:
- Add clkdev lookup support
- Update clk driver, UART driver, DTs to handle named refclk from DTs
- Split apart various clocks to more closely match hardware
- Add ethernet clocks
Cavium Octeon:
- Remove usage of cvmx_wait() in favour of __delay()
ImgTec Pistachio:
- DT: Drop deprecated dwmmc num-slots property
Ingenic JZ4780:
- Add NFS root to Ci20 defconfig
- Add watchdog to Ci20 DT & defconfig, and allow building of watchdog
driver with this SoC
Generic (multiplatform):
- Migrate xilfpga (MIPSfpga) platform to the generic platform
Lantiq xway:
- Fix ASC0/ASC1 clocks
Minor cleanups:
- Define virt_to_pfn()
- Make thread_saved_pc static
- Simplify 32-bit sign extension in __read_64bit_c0_split()
- DMA: Use vma_pages() helper
- FPU emulation: Replace unsigned with unsigned int
- MM: Removed unused lastpfn
- Alchemy: Make clk_ops const
- Lasat: Use setup_timer() helper
- ralink: Use BIT() in MT7620 PCI driver
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Merge tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips
Pull MIPS updates from James Hogan:
"These are the main MIPS changes for 4.15.
Fixes:
- ralink: Fix MT7620 PCI build issues (4.5)
- Disable cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN for 32-bit SMP
(4.1)
- Fix MIPS64 FP save/restore on 32-bit kernels (4.0)
- ptrace: Pick up ptrace/seccomp changed syscall numbers (3.19)
- ralink: Fix MT7628 pinmux (3.19)
- BCM47XX: Fix LED inversion on WRT54GSv1 (3.17)
- Fix n32 core dumping as o32 since regset support (3.13)
- ralink: Drop obsolete USB_ARCH_HAS_HCD select
Build system:
- Default to "generic" (multiplatform) system type instead of IP22
- Use generic little endian MIPS32 r2 configuration as default
defconfig instead of ip22_defconfig
FPU emulation:
- Fix exception generation for certain R6 FPU instructions
SMP:
- Allow __cpu_number_map to be larger than NR_CPUS for sparse CPU id
spaces
Miscellaneous:
- Add iomem resource for kernel bss section for kexec/kdump
- Atomics: Nudge writes on bit unlock
- DT files: Standardise "ok" -> "okay"
Minor cleanups:
- Define virt_to_pfn()
- Make thread_saved_pc static
- Simplify 32-bit sign extension in __read_64bit_c0_split()
- DMA: Use vma_pages() helper
- FPU emulation: Replace unsigned with unsigned int
- MM: Removed unused lastpfn
- Alchemy: Make clk_ops const
- Lasat: Use setup_timer() helper
- ralink: Use BIT() in MT7620 PCI driver
Platform support:
BMIPS:
- Enable HARDIRQS_SW_RESEND
Broadcom BCM63XX:
- Add clkdev lookup support
- Update clk driver, UART driver, DTs to handle named refclk from DTs
- Split apart various clocks to more closely match hardware
- Add ethernet clocks
Cavium Octeon:
- Remove usage of cvmx_wait() in favour of __delay()
ImgTec Pistachio:
- DT: Drop deprecated dwmmc num-slots property
Ingenic JZ4780:
- Add NFS root to Ci20 defconfig
- Add watchdog to Ci20 DT & defconfig, and allow building of watchdog
driver with this SoC
Generic (multiplatform):
- Migrate xilfpga (MIPSfpga) platform to the generic platform
Lantiq xway:
- Fix ASC0/ASC1 clocks"
* tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (46 commits)
MIPS: Add iomem resource for kernel bss section.
MIPS: cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN don't work for 32-bit SMP
MIPS: BMIPS: Enable HARDIRQS_SW_RESEND
MIPS: pci: Make use of the BIT() macro inside the mt7620 driver
MIPS: pci: Remove KERN_WARN instance inside the mt7620 driver
MIPS: pci: Remove duplicate define in mt7620 driver
MIPS: ralink: Fix typo in mt7628 pinmux function
MIPS: ralink: Fix MT7628 pinmux
MIPS: Fix odd fp register warnings with MIPS64r2
watchdog: jz4780: Allow selection of jz4740-wdt driver
MIPS/ptrace: Update syscall nr on register changes
MIPS/ptrace: Pick up ptrace/seccomp changed syscalls
MIPS: Fix an n32 core file generation regset support regression
MIPS: Fix MIPS64 FP save/restore on 32-bit kernels
MIPS: page.h: Define virt_to_pfn()
MIPS: Xilfpga: Switch to using generic defconfigs
MIPS: generic: Add support for MIPSfpga
MIPS: Set defconfig target to a generic system for 32r2el
MIPS: Kconfig: Set default MIPS system type as generic
MIPS: DTS: Remove num-slots from Pistachio SoC
...
This commit is contained in:
Linus Torvalds
commit
892204e06c
@ -11,6 +11,11 @@ Required properties:
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||||
- clocks: Clock driving the hardware; used to figure out the baud rate
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divisor.
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Optional properties:
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- clock-names: Should be "refclk".
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Example:
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uart0: serial@14e00520 {
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@ -19,6 +24,7 @@ Example:
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interrupt-parent = <&periph_intc>;
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interrupts = <2>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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};
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clocks {
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@ -34,7 +34,6 @@ platforms += sibyte
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platforms += sni
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platforms += txx9
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platforms += vr41xx
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platforms += xilfpga
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# include the platform specific files
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include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
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@ -65,7 +65,7 @@ config MIPS
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select HAVE_PERF_EVENTS
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select HAVE_REGS_AND_STACK_ACCESS_API
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select HAVE_SYSCALL_TRACEPOINTS
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select HAVE_VIRT_CPU_ACCOUNTING_GEN
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select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
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select IRQ_FORCED_THREADING
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select MODULES_USE_ELF_RELA if MODULES && 64BIT
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select MODULES_USE_ELF_REL if MODULES
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@ -78,7 +78,7 @@ menu "Machine selection"
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choice
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prompt "System type"
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default SGI_IP22
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default MIPS_GENERIC
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config MIPS_GENERIC
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bool "Generic board-agnostic MIPS kernel"
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@ -233,6 +233,7 @@ config BMIPS_GENERIC
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select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
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select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
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select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
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select HARDIRQS_SW_RESEND
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help
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Build a generic DT-based kernel image that boots on select
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BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
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@ -276,6 +277,7 @@ config BCM63XX
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select GPIOLIB
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select HAVE_CLK
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select MIPS_L1_CACHE_SHIFT_4
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select CLKDEV_LOOKUP
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help
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Support for BCM63XX based boards
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@ -468,29 +470,6 @@ config MACH_PISTACHIO
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help
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This enables support for the IMG Pistachio SoC platform.
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config MACH_XILFPGA
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bool "MIPSfpga Xilinx based boards"
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select BOOT_ELF32
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select BOOT_RAW
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select BUILTIN_DTB
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select CEVT_R4K
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select COMMON_CLK
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select CSRC_R4K
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select GPIOLIB
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select IRQ_MIPS_CPU
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select LIBFDT
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select MIPS_CPU_SCACHE
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select SYS_HAS_EARLY_PRINTK
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_ZBOOT_UART16550
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select USE_OF
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select USE_GENERIC_EARLY_PRINTK_8250
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select XILINX_INTC
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help
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This enables support for the IMG University Program MIPSfpga platform.
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config MIPS_MALTA
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bool "MIPS Malta board"
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select ARCH_MAY_HAVE_PC_FDC
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@ -916,7 +895,8 @@ config CAVIUM_OCTEON_SOC
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select USE_OF
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_SMP
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select NR_CPUS_DEFAULT_16
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select NR_CPUS_DEFAULT_64
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select MIPS_NR_CPU_NR_MAP_1024
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select BUILTIN_DTB
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select MTD_COMPLEX_MAPPINGS
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select SYS_SUPPORTS_RELOCATABLE
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@ -1034,7 +1014,6 @@ source "arch/mips/loongson32/Kconfig"
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source "arch/mips/loongson64/Kconfig"
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source "arch/mips/netlogic/Kconfig"
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source "arch/mips/paravirt/Kconfig"
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source "arch/mips/xilfpga/Kconfig"
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endmenu
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@ -2726,6 +2705,15 @@ config NR_CPUS
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config MIPS_PERF_SHARED_TC_COUNTERS
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bool
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config MIPS_NR_CPU_NR_MAP_1024
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bool
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config MIPS_NR_CPU_NR_MAP
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int
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depends on SMP
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default 1024 if MIPS_NR_CPU_NR_MAP_1024
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default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
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#
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# Timer Interrupt Frequency Configuration
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#
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@ -15,7 +15,7 @@
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archscripts: scripts_basic
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$(Q)$(MAKE) $(build)=arch/mips/boot/tools relocs
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KBUILD_DEFCONFIG := ip22_defconfig
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KBUILD_DEFCONFIG := 32r2el_defconfig
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#
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# Select the object file format to substitute into the linker script.
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@ -544,3 +544,7 @@ sead3_defconfig:
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.PHONY: sead3micro_defconfig
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sead3micro_defconfig:
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$(Q)$(MAKE) -f $(srctree)/Makefile micro32r2el_defconfig BOARDS=sead-3
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.PHONY: xilfpga_defconfig
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xilfpga_defconfig:
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$(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=xilfpga
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@ -143,7 +143,7 @@ void __init alchemy_set_lpj(void)
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preset_lpj /= 2 * HZ;
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}
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static struct clk_ops alchemy_clkops_cpu = {
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static const struct clk_ops alchemy_clkops_cpu = {
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.recalc_rate = alchemy_clk_cpu_recalc,
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};
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@ -224,7 +224,7 @@ static long alchemy_clk_aux_roundr(struct clk_hw *hw,
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return (*parent_rate) * mult;
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}
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static struct clk_ops alchemy_clkops_aux = {
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static const struct clk_ops alchemy_clkops_aux = {
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.recalc_rate = alchemy_clk_aux_recalc,
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.set_rate = alchemy_clk_aux_setr,
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.round_rate = alchemy_clk_aux_roundr,
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@ -576,7 +576,7 @@ static int alchemy_clk_fgv1_detr(struct clk_hw *hw,
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}
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/* Au1000, Au1100, Au15x0, Au12x0 */
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static struct clk_ops alchemy_clkops_fgenv1 = {
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static const struct clk_ops alchemy_clkops_fgenv1 = {
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.recalc_rate = alchemy_clk_fgv1_recalc,
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.determine_rate = alchemy_clk_fgv1_detr,
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.set_rate = alchemy_clk_fgv1_setr,
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@ -717,7 +717,7 @@ static int alchemy_clk_fgv2_detr(struct clk_hw *hw,
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}
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/* Au1300 larger input mux, no separate disable bit, flexible divider */
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static struct clk_ops alchemy_clkops_fgenv2 = {
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static const struct clk_ops alchemy_clkops_fgenv2 = {
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.recalc_rate = alchemy_clk_fgv2_recalc,
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.determine_rate = alchemy_clk_fgv2_detr,
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.set_rate = alchemy_clk_fgv2_setr,
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@ -925,7 +925,7 @@ static int alchemy_clk_csrc_detr(struct clk_hw *hw,
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return alchemy_clk_fgcs_detr(hw, req, scale, 4);
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}
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static struct clk_ops alchemy_clkops_csrc = {
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static const struct clk_ops alchemy_clkops_csrc = {
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.recalc_rate = alchemy_clk_csrc_recalc,
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.determine_rate = alchemy_clk_csrc_detr,
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.set_rate = alchemy_clk_csrc_setr,
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@ -331,7 +331,7 @@ bcm47xx_leds_linksys_wrt54g3gv2[] __initconst = {
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/* Verified on: WRT54GS V1.0 */
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static const struct gpio_led
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bcm47xx_leds_linksys_wrt54g_type_0101[] __initconst = {
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BCM47XX_GPIO_LED(0, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
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BCM47XX_GPIO_LED(0, "green", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
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BCM47XX_GPIO_LED(1, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
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BCM47XX_GPIO_LED(7, "green", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
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};
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@ -11,6 +11,7 @@
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#include <linux/mutex.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_io.h>
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@ -120,22 +121,57 @@ static struct clk clk_ephy = {
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.set = ephy_set,
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};
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|
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/*
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* Ethernet switch SAR clock
|
||||
*/
|
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static void swpkt_sar_set(struct clk *clk, int enable)
|
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{
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if (BCMCPU_IS_6368())
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bcm_hwclock_set(CKCTL_6368_SWPKT_SAR_EN, enable);
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else
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return;
|
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}
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|
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static struct clk clk_swpkt_sar = {
|
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.set = swpkt_sar_set,
|
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};
|
||||
|
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/*
|
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* Ethernet switch USB clock
|
||||
*/
|
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static void swpkt_usb_set(struct clk *clk, int enable)
|
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{
|
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if (BCMCPU_IS_6368())
|
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bcm_hwclock_set(CKCTL_6368_SWPKT_USB_EN, enable);
|
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else
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return;
|
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}
|
||||
|
||||
static struct clk clk_swpkt_usb = {
|
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.set = swpkt_usb_set,
|
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};
|
||||
|
||||
/*
|
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* Ethernet switch clock
|
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*/
|
||||
static void enetsw_set(struct clk *clk, int enable)
|
||||
{
|
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if (BCMCPU_IS_6328())
|
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if (BCMCPU_IS_6328()) {
|
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bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
|
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else if (BCMCPU_IS_6362())
|
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} else if (BCMCPU_IS_6362()) {
|
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bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
|
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else if (BCMCPU_IS_6368())
|
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bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
|
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CKCTL_6368_SWPKT_USB_EN |
|
||||
CKCTL_6368_SWPKT_SAR_EN,
|
||||
enable);
|
||||
else
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||||
} else if (BCMCPU_IS_6368()) {
|
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if (enable) {
|
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clk_enable_unlocked(&clk_swpkt_sar);
|
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clk_enable_unlocked(&clk_swpkt_usb);
|
||||
} else {
|
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clk_disable_unlocked(&clk_swpkt_usb);
|
||||
clk_disable_unlocked(&clk_swpkt_sar);
|
||||
}
|
||||
bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
/* reset switch core afer clock change */
|
||||
@ -247,6 +283,10 @@ static struct clk clk_hsspi = {
|
||||
.set = hsspi_set,
|
||||
};
|
||||
|
||||
/*
|
||||
* HSSPI PLL
|
||||
*/
|
||||
static struct clk clk_hsspi_pll;
|
||||
|
||||
/*
|
||||
* XTM clock
|
||||
@ -256,8 +296,12 @@ static void xtm_set(struct clk *clk, int enable)
|
||||
if (!BCMCPU_IS_6368())
|
||||
return;
|
||||
|
||||
bcm_hwclock_set(CKCTL_6368_SAR_EN |
|
||||
CKCTL_6368_SWPKT_SAR_EN, enable);
|
||||
if (enable)
|
||||
clk_enable_unlocked(&clk_swpkt_sar);
|
||||
else
|
||||
clk_disable_unlocked(&clk_swpkt_sar);
|
||||
|
||||
bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
|
||||
|
||||
if (enable) {
|
||||
/* reset sar core afer clock change */
|
||||
@ -359,44 +403,128 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_round_rate);
|
||||
|
||||
struct clk *clk_get(struct device *dev, const char *id)
|
||||
{
|
||||
if (!strcmp(id, "enet0"))
|
||||
return &clk_enet0;
|
||||
if (!strcmp(id, "enet1"))
|
||||
return &clk_enet1;
|
||||
if (!strcmp(id, "enetsw"))
|
||||
return &clk_enetsw;
|
||||
if (!strcmp(id, "ephy"))
|
||||
return &clk_ephy;
|
||||
if (!strcmp(id, "usbh"))
|
||||
return &clk_usbh;
|
||||
if (!strcmp(id, "usbd"))
|
||||
return &clk_usbd;
|
||||
if (!strcmp(id, "spi"))
|
||||
return &clk_spi;
|
||||
if (!strcmp(id, "hsspi"))
|
||||
return &clk_hsspi;
|
||||
if (!strcmp(id, "xtm"))
|
||||
return &clk_xtm;
|
||||
if (!strcmp(id, "periph"))
|
||||
return &clk_periph;
|
||||
if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
|
||||
return &clk_pcm;
|
||||
if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
|
||||
return &clk_ipsec;
|
||||
if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
|
||||
return &clk_pcie;
|
||||
return ERR_PTR(-ENOENT);
|
||||
}
|
||||
static struct clk_lookup bcm3368_clks[] = {
|
||||
/* fixed rate clocks */
|
||||
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
|
||||
/* gated clocks */
|
||||
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
|
||||
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
|
||||
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
|
||||
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||
CLKDEV_INIT(NULL, "spi", &clk_spi),
|
||||
CLKDEV_INIT(NULL, "pcm", &clk_pcm),
|
||||
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
|
||||
CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
|
||||
};
|
||||
|
||||
EXPORT_SYMBOL(clk_get);
|
||||
static struct clk_lookup bcm6328_clks[] = {
|
||||
/* fixed rate clocks */
|
||||
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
|
||||
/* gated clocks */
|
||||
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
|
||||
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||
CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
|
||||
CLKDEV_INIT(NULL, "pcie", &clk_pcie),
|
||||
};
|
||||
|
||||
void clk_put(struct clk *clk)
|
||||
{
|
||||
}
|
||||
static struct clk_lookup bcm6338_clks[] = {
|
||||
/* fixed rate clocks */
|
||||
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
||||
/* gated clocks */
|
||||
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
|
||||
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
|
||||
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
|
||||
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||
CLKDEV_INIT(NULL, "spi", &clk_spi),
|
||||
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
|
||||
};
|
||||
|
||||
EXPORT_SYMBOL(clk_put);
|
||||
static struct clk_lookup bcm6345_clks[] = {
|
||||
/* fixed rate clocks */
|
||||
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
||||
/* gated clocks */
|
||||
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
|
||||
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
|
||||
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
|
||||
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||
CLKDEV_INIT(NULL, "spi", &clk_spi),
|
||||
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
|
||||
};
|
||||
|
||||
static struct clk_lookup bcm6348_clks[] = {
|
||||
/* fixed rate clocks */
|
||||
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
||||
/* gated clocks */
|
||||
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
|
||||
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
|
||||
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
|
||||
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||
CLKDEV_INIT(NULL, "spi", &clk_spi),
|
||||
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
|
||||
CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc),
|
||||
};
|
||||
|
||||
static struct clk_lookup bcm6358_clks[] = {
|
||||
/* fixed rate clocks */
|
||||
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
|
||||
/* gated clocks */
|
||||
CLKDEV_INIT(NULL, "enet0", &clk_enet0),
|
||||
CLKDEV_INIT(NULL, "enet1", &clk_enet1),
|
||||
CLKDEV_INIT(NULL, "ephy", &clk_ephy),
|
||||
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||
CLKDEV_INIT(NULL, "spi", &clk_spi),
|
||||
CLKDEV_INIT(NULL, "pcm", &clk_pcm),
|
||||
CLKDEV_INIT(NULL, "swpkt_sar", &clk_swpkt_sar),
|
||||
CLKDEV_INIT(NULL, "swpkt_usb", &clk_swpkt_usb),
|
||||
CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
|
||||
CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
|
||||
};
|
||||
|
||||
static struct clk_lookup bcm6362_clks[] = {
|
||||
/* fixed rate clocks */
|
||||
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
|
||||
/* gated clocks */
|
||||
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
|
||||
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||
CLKDEV_INIT(NULL, "spi", &clk_spi),
|
||||
CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
|
||||
CLKDEV_INIT(NULL, "pcie", &clk_pcie),
|
||||
CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
|
||||
};
|
||||
|
||||
static struct clk_lookup bcm6368_clks[] = {
|
||||
/* fixed rate clocks */
|
||||
CLKDEV_INIT(NULL, "periph", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
|
||||
CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
|
||||
/* gated clocks */
|
||||
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
|
||||
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||
CLKDEV_INIT(NULL, "spi", &clk_spi),
|
||||
CLKDEV_INIT(NULL, "xtm", &clk_xtm),
|
||||
CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
|
||||
};
|
||||
|
||||
#define HSSPI_PLL_HZ_6328 133333333
|
||||
#define HSSPI_PLL_HZ_6362 400000000
|
||||
@ -404,11 +532,31 @@ EXPORT_SYMBOL(clk_put);
|
||||
static int __init bcm63xx_clk_init(void)
|
||||
{
|
||||
switch (bcm63xx_get_cpu_id()) {
|
||||
case BCM3368_CPU_ID:
|
||||
clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
|
||||
break;
|
||||
case BCM6328_CPU_ID:
|
||||
clk_hsspi.rate = HSSPI_PLL_HZ_6328;
|
||||
clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
|
||||
clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
|
||||
break;
|
||||
case BCM6338_CPU_ID:
|
||||
clkdev_add_table(bcm6338_clks, ARRAY_SIZE(bcm6338_clks));
|
||||
break;
|
||||
case BCM6345_CPU_ID:
|
||||
clkdev_add_table(bcm6345_clks, ARRAY_SIZE(bcm6345_clks));
|
||||
break;
|
||||
case BCM6348_CPU_ID:
|
||||
clkdev_add_table(bcm6348_clks, ARRAY_SIZE(bcm6348_clks));
|
||||
break;
|
||||
case BCM6358_CPU_ID:
|
||||
clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
|
||||
break;
|
||||
case BCM6362_CPU_ID:
|
||||
clk_hsspi.rate = HSSPI_PLL_HZ_6362;
|
||||
clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
|
||||
clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
|
||||
break;
|
||||
case BCM6368_CPU_ID:
|
||||
clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
@ -83,6 +83,7 @@ uart0: serial@fff8c100 {
|
||||
interrupts = <2>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
@ -95,6 +96,7 @@ uart1: serial@fff8c120 {
|
||||
interrupts = <3>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -19,7 +19,7 @@ chosen {
|
||||
};
|
||||
|
||||
&leds0 {
|
||||
status = "ok";
|
||||
status = "okay";
|
||||
brcm,serial-leds;
|
||||
brcm,serial-dat-low;
|
||||
brcm,serial-shift-inv;
|
||||
|
||||
@ -84,6 +84,7 @@ uart0: serial@10000180 {
|
||||
interrupts = <5>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
@ -96,6 +97,7 @@ uart1: serial@100001a0 {
|
||||
interrupts = <34>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -69,6 +69,7 @@ uart0: serial@10000100 {
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <28>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -78,6 +79,7 @@ uart1: serial@10000120 {
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <39>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -19,7 +19,7 @@ chosen {
|
||||
};
|
||||
|
||||
&leds0 {
|
||||
status = "ok";
|
||||
status = "okay";
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
|
||||
@ -93,6 +93,7 @@ uart0: serial@fffe0100 {
|
||||
interrupts = <2>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
@ -105,6 +106,7 @@ uart1: serial@fffe0120 {
|
||||
interrupts = <3>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -84,6 +84,7 @@ uart0: serial@10000100 {
|
||||
interrupts = <3>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
@ -96,6 +97,7 @@ uart1: serial@10000120 {
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -90,6 +90,7 @@ uart0: serial@10000100 {
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <2>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -99,6 +100,7 @@ uart1: serial@10000120 {
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <3>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -805,7 +805,6 @@ sdhost: mmc@18142000 {
|
||||
pinctrl-0 = <&sdhost_pins>;
|
||||
pinctrl-names = "default";
|
||||
fifo-depth = <0x20>;
|
||||
num-slots = <1>;
|
||||
clock-frequency = <50000000>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
|
||||
@ -219,6 +219,11 @@ uart4: serial@10034000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@10002000 {
|
||||
compatible = "ingenic,jz4780-watchdog";
|
||||
reg = <0x10002000 0x100>;
|
||||
};
|
||||
|
||||
nemc: nemc@13410000 {
|
||||
compatible = "ingenic,jz4780-nemc";
|
||||
reg = <0x13410000 0x10000>;
|
||||
|
||||
@ -47,6 +47,6 @@ partition@50000 {
|
||||
};
|
||||
|
||||
usb@101c0000 {
|
||||
status = "ok";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_XILFPGA_NEXYS4DDR) += nexys4ddr.dtb
|
||||
dtb-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += nexys4ddr.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
|
||||
@ -6,6 +6,14 @@
|
||||
/ {
|
||||
compatible = "digilent,nexys4ddr";
|
||||
|
||||
aliases {
|
||||
serial0 = &axi_uart16550;
|
||||
};
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
|
||||
@ -862,7 +862,7 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
|
||||
*/
|
||||
cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
|
||||
|
||||
cvmx_wait(100000000ull);
|
||||
__delay(100000000ull);
|
||||
|
||||
for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
|
||||
retry_cnt = 100000;
|
||||
|
||||
@ -215,7 +215,7 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
|
||||
spxx_clk_ctl.u64 = 0;
|
||||
spxx_clk_ctl.s.runbist = 1;
|
||||
cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
|
||||
cvmx_wait(10 * MS);
|
||||
__delay(10 * MS);
|
||||
spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
|
||||
if (spxx_bist_stat.s.stat0)
|
||||
cvmx_dprintf
|
||||
@ -265,14 +265,14 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
|
||||
spxx_clk_ctl.s.rcvtrn = 0;
|
||||
spxx_clk_ctl.s.srxdlck = 0;
|
||||
cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
|
||||
cvmx_wait(100 * MS);
|
||||
__delay(100 * MS);
|
||||
|
||||
/* Reset SRX0 DLL */
|
||||
spxx_clk_ctl.s.srxdlck = 1;
|
||||
cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
|
||||
|
||||
/* Waiting for Inf0 Spi4 RX DLL to lock */
|
||||
cvmx_wait(100 * MS);
|
||||
__delay(100 * MS);
|
||||
|
||||
/* Enable dynamic alignment */
|
||||
spxx_trn4_ctl.s.trntest = 0;
|
||||
@ -527,7 +527,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
|
||||
spxx_clk_ctl.s.rcvtrn = 1;
|
||||
spxx_clk_ctl.s.srxdlck = 1;
|
||||
cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
|
||||
cvmx_wait(1000 * MS);
|
||||
__delay(1000 * MS);
|
||||
|
||||
/* SRX0 clear the boot bit */
|
||||
spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
|
||||
@ -536,7 +536,7 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
|
||||
|
||||
/* Wait for the training sequence to complete */
|
||||
cvmx_dprintf("SPI%d: Waiting for training\n", interface);
|
||||
cvmx_wait(1000 * MS);
|
||||
__delay(1000 * MS);
|
||||
/* Wait a really long time here */
|
||||
timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;
|
||||
/*
|
||||
|
||||
@ -38,6 +38,8 @@ CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
@ -93,6 +95,8 @@ CONFIG_I2C_JZ4780=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_INGENIC=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_JZ4740_WDT=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_DEBUG=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
@ -110,7 +114,8 @@ CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
# CONFIG_NETWORK_FILESYSTEMS is not set
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_737=y
|
||||
|
||||
22
arch/mips/configs/generic/board-xilfpga.config
Normal file
22
arch/mips/configs/generic/board-xilfpga.config
Normal file
@ -0,0 +1,22 @@
|
||||
# require CONFIG_CPU_MIPS32_R2=y
|
||||
# require CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_XILINX=y
|
||||
CONFIG_PANIC_ON_OOPS=y
|
||||
CONFIG_FIT_IMAGE_FDT_XILFPGA=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_XILINX=y
|
||||
CONFIG_SENSORS_ADT7410=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_XILINX_EMACLITE=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
@ -1,3 +1,4 @@
|
||||
CONFIG_SGI_IP22=y
|
||||
CONFIG_ARC_CONSOLE=y
|
||||
CONFIG_CPU_R5000=y
|
||||
CONFIG_NO_HZ=y
|
||||
|
||||
@ -1,75 +0,0 @@
|
||||
CONFIG_MACH_XILFPGA=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_BLOCK is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FW_LOADER is not set
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_CORE is not set
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_EZCHIP is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NETRONOME is not set
|
||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
||||
# CONFIG_NET_VENDOR_RENESAS is not set
|
||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
||||
# CONFIG_NET_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_NET_VENDOR_SYNOPSYS is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_XILINX_EMACLITE=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
# CONFIG_UNIX98_PTYS is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_HELPER_AUTO is not set
|
||||
CONFIG_I2C_XILINX=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_XILINX=y
|
||||
CONFIG_SENSORS_ADT7410=y
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_MIPS_PLATFORM_DEVICES is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_PANIC_ON_OOPS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="console=ttyS0,115200"
|
||||
@ -43,4 +43,10 @@ config FIT_IMAGE_FDT_NI169445
|
||||
Enable this to include the FDT for the 169445 platform from
|
||||
National Instruments in the FIT kernel image.
|
||||
|
||||
config FIT_IMAGE_FDT_XILFPGA
|
||||
bool "Include FDT for Xilfpga"
|
||||
help
|
||||
Enable this to include the FDT for the MIPSfpga platform
|
||||
from Imagination Technologies in the FIT kernel image.
|
||||
|
||||
endif
|
||||
|
||||
22
arch/mips/generic/board-xilfpga.its.S
Normal file
22
arch/mips/generic/board-xilfpga.its.S
Normal file
@ -0,0 +1,22 @@
|
||||
/ {
|
||||
images {
|
||||
fdt@xilfpga {
|
||||
description = "MIPSfpga (xilfpga) Device Tree";
|
||||
data = /incbin/("boot/dts/xilfpga/nexys4ddr.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "mips";
|
||||
compression = "none";
|
||||
hash@0 {
|
||||
algo = "sha1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
conf@xilfpga {
|
||||
description = "MIPSfpga Linux kernel";
|
||||
kernel = "kernel@0";
|
||||
fdt = "fdt@xilfpga";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -19,6 +19,9 @@
|
||||
#include <asm/asmmacro-64.h>
|
||||
#endif
|
||||
|
||||
/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
|
||||
#undef fp
|
||||
|
||||
/*
|
||||
* Helper macros for generating raw instruction encodings.
|
||||
*/
|
||||
@ -105,6 +108,7 @@
|
||||
.macro fpu_save_16odd thread
|
||||
.set push
|
||||
.set mips64r2
|
||||
.set fp=64
|
||||
SET_HARDFLOAT
|
||||
sdc1 $f1, THREAD_FPR1(\thread)
|
||||
sdc1 $f3, THREAD_FPR3(\thread)
|
||||
@ -126,8 +130,8 @@
|
||||
.endm
|
||||
|
||||
.macro fpu_save_double thread status tmp
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
|
||||
defined(CONFIG_CPU_MIPS32_R6)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
|
||||
defined(CONFIG_CPU_MIPSR6)
|
||||
sll \tmp, \status, 5
|
||||
bgez \tmp, 10f
|
||||
fpu_save_16odd \thread
|
||||
@ -163,6 +167,7 @@
|
||||
.macro fpu_restore_16odd thread
|
||||
.set push
|
||||
.set mips64r2
|
||||
.set fp=64
|
||||
SET_HARDFLOAT
|
||||
ldc1 $f1, THREAD_FPR1(\thread)
|
||||
ldc1 $f3, THREAD_FPR3(\thread)
|
||||
@ -184,8 +189,8 @@
|
||||
.endm
|
||||
|
||||
.macro fpu_restore_double thread status tmp
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
|
||||
defined(CONFIG_CPU_MIPS32_R6)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
|
||||
defined(CONFIG_CPU_MIPSR6)
|
||||
sll \tmp, \status, 5
|
||||
bgez \tmp, 10f # 16 register mode?
|
||||
|
||||
@ -234,9 +239,6 @@
|
||||
.endm
|
||||
|
||||
#ifdef TOOLCHAIN_SUPPORTS_MSA
|
||||
/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
|
||||
#undef fp
|
||||
|
||||
.macro _cfcmsa rd, cs
|
||||
.set push
|
||||
.set mips32r2
|
||||
|
||||
@ -456,6 +456,7 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
|
||||
{
|
||||
smp_mb__before_llsc();
|
||||
__clear_bit(nr, addr);
|
||||
nudge_writes();
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -204,8 +204,10 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
|
||||
#else
|
||||
#include <asm-generic/cmpxchg-local.h>
|
||||
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
|
||||
#ifndef CONFIG_SMP
|
||||
#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#undef __scbeqz
|
||||
|
||||
|
||||
@ -1355,19 +1355,17 @@ do { \
|
||||
if (sel == 0) \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmfc0\t%M0, " #source "\n\t" \
|
||||
"dsll\t%L0, %M0, 32\n\t" \
|
||||
"dsra\t%M0, %M0, 32\n\t" \
|
||||
"dsra\t%L0, %L0, 32\n\t" \
|
||||
"dmfc0\t%L0, " #source "\n\t" \
|
||||
"dsra\t%M0, %L0, 32\n\t" \
|
||||
"sll\t%L0, %L0, 0\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (__val)); \
|
||||
else \
|
||||
__asm__ __volatile__( \
|
||||
".set\tmips64\n\t" \
|
||||
"dmfc0\t%M0, " #source ", " #sel "\n\t" \
|
||||
"dsll\t%L0, %M0, 32\n\t" \
|
||||
"dsra\t%M0, %M0, 32\n\t" \
|
||||
"dsra\t%L0, %L0, 32\n\t" \
|
||||
"dmfc0\t%L0, " #source ", " #sel "\n\t" \
|
||||
"dsra\t%M0, %L0, 32\n\t" \
|
||||
"sll\t%L0, %L0, 0\n\t" \
|
||||
".set\tmips0" \
|
||||
: "=r" (__val)); \
|
||||
local_irq_restore(__flags); \
|
||||
|
||||
@ -36,6 +36,8 @@
|
||||
#ifndef __CVMX_FPA_H__
|
||||
#define __CVMX_FPA_H__
|
||||
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <asm/octeon/cvmx-address.h>
|
||||
#include <asm/octeon/cvmx-fpa-defs.h>
|
||||
|
||||
@ -165,7 +167,7 @@ static inline void cvmx_fpa_enable(void)
|
||||
}
|
||||
|
||||
/* Enforce a 10 cycle delay between config and enable */
|
||||
cvmx_wait(10);
|
||||
__delay(10);
|
||||
}
|
||||
|
||||
/* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
|
||||
|
||||
@ -30,6 +30,7 @@
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
enum cvmx_mips_space {
|
||||
CVMX_MIPS_SPACE_XKSEG = 3LL,
|
||||
@ -428,18 +429,6 @@ static inline uint64_t cvmx_get_cycle(void)
|
||||
return cycle;
|
||||
}
|
||||
|
||||
/**
|
||||
* Wait for the specified number of cycle
|
||||
*
|
||||
*/
|
||||
static inline void cvmx_wait(uint64_t cycles)
|
||||
{
|
||||
uint64_t done = cvmx_get_cycle() + cycles;
|
||||
|
||||
while (cvmx_get_cycle() < done)
|
||||
; /* Spin */
|
||||
}
|
||||
|
||||
/**
|
||||
* Reads a chip global cycle counter. This counts CPU cycles since
|
||||
* chip reset. The counter is 64 bit.
|
||||
@ -481,7 +470,7 @@ static inline uint64_t cvmx_get_cycle_global(void)
|
||||
result = -1; \
|
||||
break; \
|
||||
} else \
|
||||
cvmx_wait(100); \
|
||||
__delay(100); \
|
||||
} \
|
||||
} while (0); \
|
||||
result; \
|
||||
|
||||
@ -240,8 +240,8 @@ static inline int pfn_valid(unsigned long pfn)
|
||||
|
||||
#endif
|
||||
|
||||
#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys((void *) \
|
||||
(kaddr))))
|
||||
#define virt_to_pfn(kaddr) PFN_DOWN(virt_to_phys((void *)(kaddr)))
|
||||
#define virt_to_page(kaddr) pfn_to_page(virt_to_pfn(kaddr))
|
||||
|
||||
extern int __virt_addr_valid(const volatile void *kaddr);
|
||||
#define virt_addr_valid(kaddr) \
|
||||
|
||||
@ -368,8 +368,6 @@ struct task_struct;
|
||||
/* Free all resources held by a thread. */
|
||||
#define release_thread(thread) do { } while(0)
|
||||
|
||||
extern unsigned long thread_saved_pc(struct task_struct *tsk);
|
||||
|
||||
/*
|
||||
* Do necessary setup to start up a newly executed thread.
|
||||
*/
|
||||
|
||||
@ -29,7 +29,7 @@ extern cpumask_t cpu_foreign_map[];
|
||||
|
||||
/* Map from cpu id to sequential logical cpu number. This will only
|
||||
not be idempotent when cpus failed to come on-line. */
|
||||
extern int __cpu_number_map[NR_CPUS];
|
||||
extern int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP];
|
||||
#define cpu_number_map(cpu) __cpu_number_map[cpu]
|
||||
|
||||
/* The reverse map from sequential logical cpu number to cpu id. */
|
||||
|
||||
@ -26,12 +26,34 @@
|
||||
#define __NR_syscall 4000
|
||||
#endif
|
||||
|
||||
static inline bool mips_syscall_is_indirect(struct task_struct *task,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
/* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
|
||||
return (IS_ENABLED(CONFIG_32BIT) ||
|
||||
test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
|
||||
(regs->regs[2] == __NR_syscall);
|
||||
}
|
||||
|
||||
static inline long syscall_get_nr(struct task_struct *task,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
return current_thread_info()->syscall;
|
||||
}
|
||||
|
||||
static inline void mips_syscall_update_nr(struct task_struct *task,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
/*
|
||||
* v0 is the system call number, except for O32 ABI syscall(), where it
|
||||
* ends up in a0.
|
||||
*/
|
||||
if (mips_syscall_is_indirect(task, regs))
|
||||
task_thread_info(task)->syscall = regs->regs[4];
|
||||
else
|
||||
task_thread_info(task)->syscall = regs->regs[2];
|
||||
}
|
||||
|
||||
static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
|
||||
struct task_struct *task, struct pt_regs *regs, unsigned int n)
|
||||
{
|
||||
@ -98,10 +120,9 @@ static inline void syscall_get_arguments(struct task_struct *task,
|
||||
unsigned long *args)
|
||||
{
|
||||
int ret;
|
||||
/* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
|
||||
if ((IS_ENABLED(CONFIG_32BIT) ||
|
||||
test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
|
||||
(regs->regs[2] == __NR_syscall))
|
||||
|
||||
/* O32 ABI syscall() */
|
||||
if (mips_syscall_is_indirect(task, regs))
|
||||
i++;
|
||||
|
||||
while (n--)
|
||||
|
||||
@ -487,7 +487,7 @@ arch_initcall(frame_info_init);
|
||||
/*
|
||||
* Return saved PC of a blocked thread.
|
||||
*/
|
||||
unsigned long thread_saved_pc(struct task_struct *tsk)
|
||||
static unsigned long thread_saved_pc(struct task_struct *tsk)
|
||||
{
|
||||
struct thread_struct *t = &tsk->thread;
|
||||
|
||||
|
||||
@ -144,6 +144,9 @@ int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data)
|
||||
|
||||
/* badvaddr, status, and cause may not be written. */
|
||||
|
||||
/* System call number may have been changed */
|
||||
mips_syscall_update_nr(child, regs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -345,6 +348,9 @@ static int gpr32_set(struct task_struct *target,
|
||||
}
|
||||
}
|
||||
|
||||
/* System call number may have been changed */
|
||||
mips_syscall_update_nr(target, regs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -405,6 +411,9 @@ static int gpr64_set(struct task_struct *target,
|
||||
}
|
||||
}
|
||||
|
||||
/* System call number may have been changed */
|
||||
mips_syscall_update_nr(target, regs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -618,6 +627,19 @@ static const struct user_regset_view user_mips64_view = {
|
||||
.n = ARRAY_SIZE(mips64_regsets),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MIPS32_N32
|
||||
|
||||
static const struct user_regset_view user_mipsn32_view = {
|
||||
.name = "mipsn32",
|
||||
.e_flags = EF_MIPS_ABI2,
|
||||
.e_machine = ELF_ARCH,
|
||||
.ei_osabi = ELF_OSABI,
|
||||
.regsets = mips64_regsets,
|
||||
.n = ARRAY_SIZE(mips64_regsets),
|
||||
};
|
||||
|
||||
#endif /* CONFIG_MIPS32_N32 */
|
||||
|
||||
#endif /* CONFIG_64BIT */
|
||||
|
||||
const struct user_regset_view *task_user_regset_view(struct task_struct *task)
|
||||
@ -628,6 +650,10 @@ const struct user_regset_view *task_user_regset_view(struct task_struct *task)
|
||||
#ifdef CONFIG_MIPS32_O32
|
||||
if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
|
||||
return &user_mips_view;
|
||||
#endif
|
||||
#ifdef CONFIG_MIPS32_N32
|
||||
if (test_tsk_thread_flag(task, TIF_32BIT_ADDR))
|
||||
return &user_mipsn32_view;
|
||||
#endif
|
||||
return &user_mips64_view;
|
||||
#endif
|
||||
@ -753,6 +779,12 @@ long arch_ptrace(struct task_struct *child, long request,
|
||||
switch (addr) {
|
||||
case 0 ... 31:
|
||||
regs->regs[addr] = data;
|
||||
/* System call number may have been changed */
|
||||
if (addr == 2)
|
||||
mips_syscall_update_nr(child, regs);
|
||||
else if (addr == 4 &&
|
||||
mips_syscall_is_indirect(child, regs))
|
||||
mips_syscall_update_nr(child, regs);
|
||||
break;
|
||||
case FPR_BASE ... FPR_BASE + 31: {
|
||||
union fpureg *fregs = get_fpu_regs(child);
|
||||
@ -864,9 +896,11 @@ asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
|
||||
|
||||
current_thread_info()->syscall = syscall;
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE) &&
|
||||
tracehook_report_syscall_entry(regs))
|
||||
return -1;
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE)) {
|
||||
if (tracehook_report_syscall_entry(regs))
|
||||
return -1;
|
||||
syscall = current_thread_info()->syscall;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SECCOMP
|
||||
if (unlikely(test_thread_flag(TIF_SECCOMP))) {
|
||||
@ -884,6 +918,7 @@ asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
|
||||
ret = __secure_computing(&sd);
|
||||
if (ret == -1)
|
||||
return ret;
|
||||
syscall = current_thread_info()->syscall;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -33,6 +33,7 @@
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/reg.h>
|
||||
#include <asm/syscall.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
@ -195,6 +196,12 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
||||
switch (addr) {
|
||||
case 0 ... 31:
|
||||
regs->regs[addr] = data;
|
||||
/* System call number may have been changed */
|
||||
if (addr == 2)
|
||||
mips_syscall_update_nr(child, regs);
|
||||
else if (addr == 4 &&
|
||||
mips_syscall_is_indirect(child, regs))
|
||||
mips_syscall_update_nr(child, regs);
|
||||
break;
|
||||
case FPR_BASE ... FPR_BASE + 31: {
|
||||
union fpureg *fregs = get_fpu_regs(child);
|
||||
|
||||
@ -40,8 +40,8 @@
|
||||
*/
|
||||
LEAF(_save_fp)
|
||||
EXPORT_SYMBOL(_save_fp)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
|
||||
defined(CONFIG_CPU_MIPS32_R6)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
|
||||
defined(CONFIG_CPU_MIPSR6)
|
||||
mfc0 t0, CP0_STATUS
|
||||
#endif
|
||||
fpu_save_double a0 t0 t1 # clobbers t1
|
||||
@ -52,8 +52,8 @@ EXPORT_SYMBOL(_save_fp)
|
||||
* Restore a thread's fp context.
|
||||
*/
|
||||
LEAF(_restore_fp)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
|
||||
defined(CONFIG_CPU_MIPS32_R6)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
|
||||
defined(CONFIG_CPU_MIPSR6)
|
||||
mfc0 t0, CP0_STATUS
|
||||
#endif
|
||||
fpu_restore_double a0 t0 t1 # clobbers t1
|
||||
@ -246,11 +246,11 @@ LEAF(_save_fp_context)
|
||||
cfc1 t1, fcr31
|
||||
.set pop
|
||||
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
|
||||
defined(CONFIG_CPU_MIPS32_R6)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
|
||||
defined(CONFIG_CPU_MIPSR6)
|
||||
.set push
|
||||
SET_HARDFLOAT
|
||||
#ifdef CONFIG_CPU_MIPS32_R2
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
.set mips32r2
|
||||
.set fp=64
|
||||
mfc0 t0, CP0_STATUS
|
||||
@ -314,11 +314,11 @@ LEAF(_save_fp_context)
|
||||
LEAF(_restore_fp_context)
|
||||
EX lw t1, 0(a1)
|
||||
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
|
||||
defined(CONFIG_CPU_MIPS32_R6)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
|
||||
defined(CONFIG_CPU_MIPSR6)
|
||||
.set push
|
||||
SET_HARDFLOAT
|
||||
#ifdef CONFIG_CPU_MIPS32_R2
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
.set mips32r2
|
||||
.set fp=64
|
||||
mfc0 t0, CP0_STATUS
|
||||
|
||||
@ -80,6 +80,7 @@ EXPORT_SYMBOL(mips_io_port_base);
|
||||
|
||||
static struct resource code_resource = { .name = "Kernel code", };
|
||||
static struct resource data_resource = { .name = "Kernel data", };
|
||||
static struct resource bss_resource = { .name = "Kernel bss", };
|
||||
|
||||
static void *detect_magic __initdata = detect_memory_region;
|
||||
|
||||
@ -927,6 +928,8 @@ static void __init resource_init(void)
|
||||
code_resource.end = __pa_symbol(&_etext) - 1;
|
||||
data_resource.start = __pa_symbol(&_etext);
|
||||
data_resource.end = __pa_symbol(&_edata) - 1;
|
||||
bss_resource.start = __pa_symbol(&__bss_start);
|
||||
bss_resource.end = __pa_symbol(&__bss_stop) - 1;
|
||||
|
||||
for (i = 0; i < boot_mem_map.nr_map; i++) {
|
||||
struct resource *res;
|
||||
@ -966,6 +969,7 @@ static void __init resource_init(void)
|
||||
*/
|
||||
request_resource(res, &code_resource);
|
||||
request_resource(res, &data_resource);
|
||||
request_resource(res, &bss_resource);
|
||||
request_crashkernel(res);
|
||||
}
|
||||
}
|
||||
|
||||
@ -48,7 +48,7 @@
|
||||
#include <asm/setup.h>
|
||||
#include <asm/maar.h>
|
||||
|
||||
int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
|
||||
int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP]; /* Map physical to logical */
|
||||
EXPORT_SYMBOL(__cpu_number_map);
|
||||
|
||||
int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
|
||||
|
||||
@ -446,9 +446,9 @@ void __init ltq_soc_init(void)
|
||||
|
||||
/* add our generic xway clocks */
|
||||
clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
|
||||
clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
|
||||
clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
|
||||
clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
|
||||
clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
|
||||
clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
|
||||
clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
|
||||
clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
|
||||
@ -462,10 +462,8 @@ void __init ltq_soc_init(void)
|
||||
clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
|
||||
}
|
||||
|
||||
if (!of_machine_is_compatible("lantiq,ase")) {
|
||||
clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
|
||||
if (!of_machine_is_compatible("lantiq,ase"))
|
||||
clkdev_add_pci();
|
||||
}
|
||||
|
||||
if (of_machine_is_compatible("lantiq,grx390") ||
|
||||
of_machine_is_compatible("lantiq,ar10")) {
|
||||
|
||||
@ -197,8 +197,7 @@ static int __init pvc_proc_init(void)
|
||||
if (proc_entry == NULL)
|
||||
goto error;
|
||||
|
||||
init_timer(&timer);
|
||||
timer.function = pvc_proc_timerfunc;
|
||||
setup_timer(&timer, pvc_proc_timerfunc, 0UL);
|
||||
|
||||
return 0;
|
||||
error:
|
||||
|
||||
@ -810,7 +810,7 @@ do { \
|
||||
#define SITOREG(si, x) \
|
||||
do { \
|
||||
if (cop1_64bit(xcp) && !hybrid_fprs()) { \
|
||||
unsigned i; \
|
||||
unsigned int i; \
|
||||
set_fpr32(&ctx->fpr[x], 0, si); \
|
||||
for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
|
||||
set_fpr32(&ctx->fpr[x], i, 0); \
|
||||
@ -823,7 +823,7 @@ do { \
|
||||
|
||||
#define SITOHREG(si, x) \
|
||||
do { \
|
||||
unsigned i; \
|
||||
unsigned int i; \
|
||||
set_fpr32(&ctx->fpr[x], 1, si); \
|
||||
for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
|
||||
set_fpr32(&ctx->fpr[x], i, 0); \
|
||||
@ -834,7 +834,7 @@ do { \
|
||||
|
||||
#define DITOREG(di, x) \
|
||||
do { \
|
||||
unsigned fpr, i; \
|
||||
unsigned int fpr, i; \
|
||||
fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \
|
||||
set_fpr64(&ctx->fpr[fpr], 0, di); \
|
||||
for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
|
||||
@ -1465,7 +1465,7 @@ DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
|
||||
static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
mips_instruction ir, void __user **fault_addr)
|
||||
{
|
||||
unsigned rcsr = 0; /* resulting csr */
|
||||
unsigned int rcsr = 0; /* resulting csr */
|
||||
|
||||
MIPS_FPU_EMU_INC_STATS(cp1xops);
|
||||
|
||||
@ -1661,10 +1661,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
mips_instruction ir)
|
||||
{
|
||||
int rfmt; /* resulting format */
|
||||
unsigned rcsr = 0; /* resulting csr */
|
||||
unsigned int rcsr = 0; /* resulting csr */
|
||||
unsigned int oldrm;
|
||||
unsigned int cbit;
|
||||
unsigned cond;
|
||||
unsigned int cond;
|
||||
union {
|
||||
union ieee754dp d;
|
||||
union ieee754sp s;
|
||||
@ -1795,7 +1795,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
SPFROMREG(fs, MIPSInst_FS(ir));
|
||||
SPFROMREG(fd, MIPSInst_FD(ir));
|
||||
rv.s = ieee754sp_maddf(fd, fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmsubf_op: {
|
||||
@ -1809,7 +1809,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
SPFROMREG(fs, MIPSInst_FS(ir));
|
||||
SPFROMREG(fd, MIPSInst_FD(ir));
|
||||
rv.s = ieee754sp_msubf(fd, fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case frint_op: {
|
||||
@ -1834,7 +1834,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
SPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.w = ieee754sp_2008class(fs);
|
||||
rfmt = w_fmt;
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmin_op: {
|
||||
@ -1847,7 +1847,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
SPFROMREG(ft, MIPSInst_FT(ir));
|
||||
SPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.s = ieee754sp_fmin(fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmina_op: {
|
||||
@ -1860,7 +1860,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
SPFROMREG(ft, MIPSInst_FT(ir));
|
||||
SPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.s = ieee754sp_fmina(fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmax_op: {
|
||||
@ -1873,7 +1873,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
SPFROMREG(ft, MIPSInst_FT(ir));
|
||||
SPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.s = ieee754sp_fmax(fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmaxa_op: {
|
||||
@ -1886,7 +1886,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
SPFROMREG(ft, MIPSInst_FT(ir));
|
||||
SPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.s = ieee754sp_fmaxa(fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fabs_op:
|
||||
@ -2029,9 +2029,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
|
||||
default:
|
||||
if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
|
||||
unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
||||
unsigned int cmpop;
|
||||
union ieee754sp fs, ft;
|
||||
|
||||
cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
||||
SPFROMREG(fs, MIPSInst_FS(ir));
|
||||
SPFROMREG(ft, MIPSInst_FT(ir));
|
||||
rv.w = ieee754sp_cmp(fs, ft,
|
||||
@ -2165,7 +2166,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
DPFROMREG(fd, MIPSInst_FD(ir));
|
||||
rv.d = ieee754dp_maddf(fd, fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmsubf_op: {
|
||||
@ -2179,7 +2180,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
DPFROMREG(fd, MIPSInst_FD(ir));
|
||||
rv.d = ieee754dp_msubf(fd, fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case frint_op: {
|
||||
@ -2204,7 +2205,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.l = ieee754dp_2008class(fs);
|
||||
rfmt = l_fmt;
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmin_op: {
|
||||
@ -2217,7 +2218,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
DPFROMREG(ft, MIPSInst_FT(ir));
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.d = ieee754dp_fmin(fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmina_op: {
|
||||
@ -2230,7 +2231,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
DPFROMREG(ft, MIPSInst_FT(ir));
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.d = ieee754dp_fmina(fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmax_op: {
|
||||
@ -2243,7 +2244,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
DPFROMREG(ft, MIPSInst_FT(ir));
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.d = ieee754dp_fmax(fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fmaxa_op: {
|
||||
@ -2256,7 +2257,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
DPFROMREG(ft, MIPSInst_FT(ir));
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
rv.d = ieee754dp_fmaxa(fs, ft);
|
||||
break;
|
||||
goto copcsr;
|
||||
}
|
||||
|
||||
case fabs_op:
|
||||
@ -2379,9 +2380,10 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
||||
|
||||
default:
|
||||
if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
|
||||
unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
||||
unsigned int cmpop;
|
||||
union ieee754dp fs, ft;
|
||||
|
||||
cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
||||
DPFROMREG(fs, MIPSInst_FS(ir));
|
||||
DPFROMREG(ft, MIPSInst_FT(ir));
|
||||
rv.w = ieee754dp_cmp(fs, ft,
|
||||
|
||||
@ -45,10 +45,10 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
|
||||
{
|
||||
int re;
|
||||
int rs;
|
||||
unsigned lxm;
|
||||
unsigned hxm;
|
||||
unsigned lym;
|
||||
unsigned hym;
|
||||
unsigned int lxm;
|
||||
unsigned int hxm;
|
||||
unsigned int lym;
|
||||
unsigned int hym;
|
||||
u64 lrm;
|
||||
u64 hrm;
|
||||
u64 lzm;
|
||||
|
||||
@ -26,10 +26,10 @@ union ieee754dp ieee754dp_mul(union ieee754dp x, union ieee754dp y)
|
||||
int re;
|
||||
int rs;
|
||||
u64 rm;
|
||||
unsigned lxm;
|
||||
unsigned hxm;
|
||||
unsigned lym;
|
||||
unsigned hym;
|
||||
unsigned int lxm;
|
||||
unsigned int hxm;
|
||||
unsigned int lym;
|
||||
unsigned int hym;
|
||||
u64 lrm;
|
||||
u64 hrm;
|
||||
u64 t;
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
|
||||
#include "ieee754dp.h"
|
||||
|
||||
static const unsigned table[] = {
|
||||
static const unsigned int table[] = {
|
||||
0, 1204, 3062, 5746, 9193, 13348, 18162, 23592,
|
||||
29598, 36145, 43202, 50740, 58733, 67158, 75992,
|
||||
85215, 83599, 71378, 60428, 50647, 41945, 34246,
|
||||
@ -33,7 +33,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x)
|
||||
{
|
||||
struct _ieee754_csr oldcsr;
|
||||
union ieee754dp y, z, t;
|
||||
unsigned scalx, yh;
|
||||
unsigned int scalx, yh;
|
||||
COMPXDP;
|
||||
|
||||
EXPLODEXDP;
|
||||
|
||||
@ -165,11 +165,12 @@ struct _ieee754_csr {
|
||||
};
|
||||
#define ieee754_csr (*(struct _ieee754_csr *)(¤t->thread.fpu.fcr31))
|
||||
|
||||
static inline unsigned ieee754_getrm(void)
|
||||
static inline unsigned int ieee754_getrm(void)
|
||||
{
|
||||
return (ieee754_csr.rm);
|
||||
}
|
||||
static inline unsigned ieee754_setrm(unsigned rm)
|
||||
|
||||
static inline unsigned int ieee754_setrm(unsigned int rm)
|
||||
{
|
||||
return (ieee754_csr.rm = rm);
|
||||
}
|
||||
@ -177,14 +178,14 @@ static inline unsigned ieee754_setrm(unsigned rm)
|
||||
/*
|
||||
* get current exceptions
|
||||
*/
|
||||
static inline unsigned ieee754_getcx(void)
|
||||
static inline unsigned int ieee754_getcx(void)
|
||||
{
|
||||
return (ieee754_csr.cx);
|
||||
}
|
||||
|
||||
/* test for current exception condition
|
||||
*/
|
||||
static inline int ieee754_cxtest(unsigned n)
|
||||
static inline int ieee754_cxtest(unsigned int n)
|
||||
{
|
||||
return (ieee754_csr.cx & n);
|
||||
}
|
||||
@ -192,21 +193,21 @@ static inline int ieee754_cxtest(unsigned n)
|
||||
/*
|
||||
* get sticky exceptions
|
||||
*/
|
||||
static inline unsigned ieee754_getsx(void)
|
||||
static inline unsigned int ieee754_getsx(void)
|
||||
{
|
||||
return (ieee754_csr.sx);
|
||||
}
|
||||
|
||||
/* clear sticky conditions
|
||||
*/
|
||||
static inline unsigned ieee754_clrsx(void)
|
||||
static inline unsigned int ieee754_clrsx(void)
|
||||
{
|
||||
return (ieee754_csr.sx = 0);
|
||||
}
|
||||
|
||||
/* test for sticky exception condition
|
||||
*/
|
||||
static inline int ieee754_sxtest(unsigned n)
|
||||
static inline int ieee754_sxtest(unsigned int n)
|
||||
{
|
||||
return (ieee754_csr.sx & n);
|
||||
}
|
||||
|
||||
@ -54,13 +54,13 @@ static inline int ieee754_class_nan(int xc)
|
||||
}
|
||||
|
||||
#define COMPXSP \
|
||||
unsigned xm; int xe; int xs __maybe_unused; int xc
|
||||
unsigned int xm; int xe; int xs __maybe_unused; int xc
|
||||
|
||||
#define COMPYSP \
|
||||
unsigned ym; int ye; int ys; int yc
|
||||
unsigned int ym; int ye; int ys; int yc
|
||||
|
||||
#define COMPZSP \
|
||||
unsigned zm; int ze; int zs; int zc
|
||||
unsigned int zm; int ze; int zs; int zc
|
||||
|
||||
#define EXPLODESP(v, vc, vs, ve, vm) \
|
||||
{ \
|
||||
|
||||
@ -65,7 +65,7 @@ union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r)
|
||||
return r;
|
||||
}
|
||||
|
||||
static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
|
||||
static unsigned int ieee754sp_get_rounding(int sn, unsigned int xm)
|
||||
{
|
||||
/* inexact must round of 3 bits
|
||||
*/
|
||||
@ -96,7 +96,7 @@ static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
|
||||
* xe is an unbiased exponent
|
||||
* xm is 3bit extended precision value.
|
||||
*/
|
||||
union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
|
||||
union ieee754sp ieee754sp_format(int sn, int xe, unsigned int xm)
|
||||
{
|
||||
assert(xm); /* we don't gen exact zeros (probably should) */
|
||||
|
||||
|
||||
@ -69,7 +69,7 @@ static inline int ieee754sp_finite(union ieee754sp x)
|
||||
#define SPDNORMY SPDNORMx(ym, ye)
|
||||
#define SPDNORMZ SPDNORMx(zm, ze)
|
||||
|
||||
static inline union ieee754sp buildsp(int s, int bx, unsigned m)
|
||||
static inline union ieee754sp buildsp(int s, int bx, unsigned int m)
|
||||
{
|
||||
union ieee754sp r;
|
||||
|
||||
|
||||
@ -23,9 +23,9 @@
|
||||
|
||||
union ieee754sp ieee754sp_div(union ieee754sp x, union ieee754sp y)
|
||||
{
|
||||
unsigned rm;
|
||||
unsigned int rm;
|
||||
int re;
|
||||
unsigned bm;
|
||||
unsigned int bm;
|
||||
|
||||
COMPXSP;
|
||||
COMPYSP;
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
|
||||
union ieee754sp ieee754sp_fint(int x)
|
||||
{
|
||||
unsigned xm;
|
||||
unsigned int xm;
|
||||
int xe;
|
||||
int xs;
|
||||
|
||||
|
||||
@ -20,9 +20,9 @@ static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
|
||||
{
|
||||
int re;
|
||||
int rs;
|
||||
unsigned rm;
|
||||
uint64_t rm64;
|
||||
uint64_t zm64;
|
||||
unsigned int rm;
|
||||
u64 rm64;
|
||||
u64 zm64;
|
||||
int s;
|
||||
|
||||
COMPXSP;
|
||||
|
||||
@ -25,15 +25,15 @@ union ieee754sp ieee754sp_mul(union ieee754sp x, union ieee754sp y)
|
||||
{
|
||||
int re;
|
||||
int rs;
|
||||
unsigned rm;
|
||||
unsigned int rm;
|
||||
unsigned short lxm;
|
||||
unsigned short hxm;
|
||||
unsigned short lym;
|
||||
unsigned short hym;
|
||||
unsigned lrm;
|
||||
unsigned hrm;
|
||||
unsigned t;
|
||||
unsigned at;
|
||||
unsigned int lrm;
|
||||
unsigned int hrm;
|
||||
unsigned int t;
|
||||
unsigned int at;
|
||||
|
||||
COMPXSP;
|
||||
COMPYSP;
|
||||
|
||||
@ -179,7 +179,7 @@ static int mips_dma_mmap(struct device *dev, struct vm_area_struct *vma,
|
||||
void *cpu_addr, dma_addr_t dma_addr, size_t size,
|
||||
unsigned long attrs)
|
||||
{
|
||||
unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
|
||||
unsigned long user_count = vma_pages(vma);
|
||||
unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
||||
unsigned long addr = (unsigned long)cpu_addr;
|
||||
unsigned long off = vma->vm_pgoff;
|
||||
|
||||
@ -402,7 +402,6 @@ int page_is_ram(unsigned long pagenr)
|
||||
void __init paging_init(void)
|
||||
{
|
||||
unsigned long max_zone_pfns[MAX_NR_ZONES];
|
||||
unsigned long lastpfn __maybe_unused;
|
||||
|
||||
pagetable_init();
|
||||
|
||||
@ -416,17 +415,14 @@ void __init paging_init(void)
|
||||
max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
|
||||
#endif
|
||||
max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
|
||||
lastpfn = max_low_pfn;
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
|
||||
lastpfn = highend_pfn;
|
||||
|
||||
if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
|
||||
printk(KERN_WARNING "This processor doesn't support highmem."
|
||||
" %ldk highmem ignored\n",
|
||||
(highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
|
||||
max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
|
||||
lastpfn = max_low_pfn;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -33,14 +33,13 @@
|
||||
#define RALINK_GPIOMODE 0x60
|
||||
|
||||
#define PPLL_CFG1 0x9c
|
||||
#define PDRV_SW_SET BIT(23)
|
||||
|
||||
#define PPLL_DRV 0xa0
|
||||
#define PDRV_SW_SET (1<<31)
|
||||
#define LC_CKDRVPD (1<<19)
|
||||
#define LC_CKDRVOHZ (1<<18)
|
||||
#define LC_CKDRVHZ (1<<17)
|
||||
#define LC_CKTEST (1<<16)
|
||||
#define PDRV_SW_SET BIT(31)
|
||||
#define LC_CKDRVPD BIT(19)
|
||||
#define LC_CKDRVOHZ BIT(18)
|
||||
#define LC_CKDRVHZ BIT(17)
|
||||
#define LC_CKTEST BIT(16)
|
||||
|
||||
/* PCI Bridge registers */
|
||||
#define RALINK_PCI_PCICFG_ADDR 0x00
|
||||
@ -66,7 +65,7 @@
|
||||
#define PCIEPHY0_CFG 0x90
|
||||
|
||||
#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
|
||||
#define RALINK_PCIE0_CLK_EN (1 << 26)
|
||||
#define RALINK_PCIE0_CLK_EN BIT(26)
|
||||
|
||||
#define BUSY 0x80000000
|
||||
#define WAITRETRY_MAX 10
|
||||
@ -121,7 +120,7 @@ static int wait_pciephy_busy(void)
|
||||
else
|
||||
break;
|
||||
if (retry++ > WAITRETRY_MAX) {
|
||||
printk(KERN_WARN "PCIE-PHY retry failed.\n");
|
||||
pr_warn("PCIE-PHY retry failed.\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
@ -639,7 +639,7 @@ static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
|
||||
cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
|
||||
return -1;
|
||||
}
|
||||
cvmx_wait(10000);
|
||||
__delay(10000);
|
||||
pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
|
||||
} while (pciercx_cfg032.s.dlla == 0);
|
||||
|
||||
@ -821,7 +821,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
|
||||
* don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
|
||||
* fixed number of cycles.
|
||||
*/
|
||||
cvmx_wait(400000);
|
||||
__delay(400000);
|
||||
|
||||
/*
|
||||
* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
|
||||
@ -1018,7 +1018,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
|
||||
i = in_p_offset;
|
||||
while (i--) {
|
||||
cvmx_write64_uint32(write_address, 0);
|
||||
cvmx_wait(10000);
|
||||
__delay(10000);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1034,7 +1034,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
|
||||
dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
|
||||
old_in_fif_p_count = dbg_data.s.data & 0xff;
|
||||
cvmx_write64_uint32(write_address, 0);
|
||||
cvmx_wait(10000);
|
||||
__delay(10000);
|
||||
dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
|
||||
in_fif_p_count = dbg_data.s.data & 0xff;
|
||||
} while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
|
||||
@ -1053,7 +1053,7 @@ static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
|
||||
cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
|
||||
while (in_fif_p_count != 0) {
|
||||
cvmx_write64_uint32(write_address, 0);
|
||||
cvmx_wait(10000);
|
||||
__delay(10000);
|
||||
in_fif_p_count = (in_fif_p_count + 1) & 0xff;
|
||||
}
|
||||
/*
|
||||
@ -1105,7 +1105,7 @@ static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
|
||||
do {
|
||||
if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
|
||||
return -1;
|
||||
cvmx_wait(10000);
|
||||
__delay(10000);
|
||||
pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
|
||||
} while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
|
||||
|
||||
|
||||
@ -31,7 +31,6 @@ choice
|
||||
|
||||
config SOC_RT305X
|
||||
bool "RT305x"
|
||||
select USB_ARCH_HAS_HCD
|
||||
|
||||
config SOC_RT3883
|
||||
bool "RT3883"
|
||||
|
||||
@ -145,8 +145,8 @@ static struct rt2880_pmx_func i2c_grp_mt7628[] = {
|
||||
FUNC("i2c", 0, 4, 2),
|
||||
};
|
||||
|
||||
static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
|
||||
static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
|
||||
static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) };
|
||||
static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) };
|
||||
static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) };
|
||||
static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
|
||||
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
choice
|
||||
prompt "Machine type"
|
||||
depends on MACH_XILFPGA
|
||||
default XILFPGA_NEXYS4DDR
|
||||
|
||||
config XILFPGA_NEXYS4DDR
|
||||
bool "Nexys4DDR by Digilent"
|
||||
|
||||
endchoice
|
||||
@ -1,7 +0,0 @@
|
||||
#
|
||||
# Makefile for the Xilfpga
|
||||
#
|
||||
|
||||
obj-y += init.o
|
||||
obj-y += intc.o
|
||||
obj-y += time.o
|
||||
@ -1,3 +0,0 @@
|
||||
platform-$(CONFIG_MACH_XILFPGA) += xilfpga/
|
||||
cflags-$(CONFIG_MACH_XILFPGA) += -I$(srctree)/arch/mips/include/asm/mach-xilfpga
|
||||
load-$(CONFIG_MACH_XILFPGA) += 0xffffffff80100000
|
||||
@ -1,44 +0,0 @@
|
||||
/*
|
||||
* Xilfpga platform setup
|
||||
*
|
||||
* Copyright (C) 2015 Imagination Technologies
|
||||
* Author: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/of_fdt.h>
|
||||
|
||||
#include <asm/prom.h>
|
||||
|
||||
#define XILFPGA_UART_BASE 0xb0401000
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "MIPSfpga";
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
__dt_setup_arch(__dtb_start);
|
||||
strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
setup_8250_early_printk_port(XILFPGA_UART_BASE, 2, 50000);
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
if (!initial_boot_params)
|
||||
return;
|
||||
|
||||
unflatten_and_copy_device_tree();
|
||||
}
|
||||
@ -1,22 +0,0 @@
|
||||
/*
|
||||
* Xilfpga interrupt controller setup
|
||||
*
|
||||
* Copyright (C) 2015 Imagination Technologies
|
||||
* Author: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
|
||||
#include <asm/irq_cpu.h>
|
||||
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
irqchip_init();
|
||||
}
|
||||
@ -1,41 +0,0 @@
|
||||
/*
|
||||
* Xilfpga clocksource/timer setup
|
||||
*
|
||||
* Copyright (C) 2015 Imagination Technologies
|
||||
* Author: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct clk *clk;
|
||||
|
||||
of_clk_init(NULL);
|
||||
timer_probe();
|
||||
|
||||
np = of_get_cpu_node(0, NULL);
|
||||
if (!np) {
|
||||
pr_err("Failed to get CPU node\n");
|
||||
return;
|
||||
}
|
||||
|
||||
clk = of_clk_get(np, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
|
||||
return;
|
||||
}
|
||||
|
||||
mips_hpt_frequency = clk_get_rate(clk) / 2;
|
||||
clk_put(clk);
|
||||
}
|
||||
@ -843,8 +843,10 @@ static int bcm_uart_probe(struct platform_device *pdev)
|
||||
if (!res_irq)
|
||||
return -ENODEV;
|
||||
|
||||
clk = pdev->dev.of_node ? of_clk_get(pdev->dev.of_node, 0) :
|
||||
clk_get(&pdev->dev, "periph");
|
||||
clk = clk_get(&pdev->dev, "refclk");
|
||||
if (IS_ERR(clk) && pdev->dev.of_node)
|
||||
clk = of_clk_get(pdev->dev.of_node, 0);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
return -ENODEV;
|
||||
|
||||
|
||||
@ -1460,7 +1460,7 @@ config INDYDOG
|
||||
|
||||
config JZ4740_WDT
|
||||
tristate "Ingenic jz4740 SoC hardware watchdog"
|
||||
depends on MACH_JZ4740
|
||||
depends on MACH_JZ4740 || MACH_JZ4780
|
||||
select WATCHDOG_CORE
|
||||
help
|
||||
Hardware driver for the built-in watchdog timer on Ingenic jz4740 SoCs.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user