AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-12 14:06:39 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

cxgb3: fix Gen2 pci default settings

Browse Source 
Modify control register settings to accommodate the bridge's max read
requset size.

Signed-off-by: Divy Le Ray <divy@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Divy Le Ray 2009-07-30 21:23:39 +00:00 committed by David S. Miller
parent 9450526ac7
commit 88e7b76ef7
1 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/net/cxgb3/t3_hw.c
View File

@ -3465,7 +3465,7 @@ static void config_pcie(struct adapter *adap)
{201, 321, 258, 450, 834, 1602}
};
u16 val;
u16 val, devid;
unsigned int log2_width, pldsize;
unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
@ -3473,6 +3473,17 @@ static void config_pcie(struct adapter *adap)
adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
&val);
pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
pci_read_config_word(adap->pdev, 0x2, &devid);
if (devid == 0x37) {
pci_write_config_word(adap->pdev,
adap->params.pci.pcie_cap_addr +
PCI_EXP_DEVCTL,
val & ~PCI_EXP_DEVCTL_READRQ &
~PCI_EXP_DEVCTL_PAYLOAD);
pldsize = 0;
}
pci_read_config_word(adap->pdev,
adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,
&val);