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mmc: mediatek: command queue support
Support command queue for mt6779 platform. a. Add msdc_set_busy_timeout() to calculate emmc write timeout. b. Connect mtk msdc driver to cqhci driver through host->cq_host->ops = &msdc_cmdq_ops; c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. d. Select kernel config MMC_CQHCI for MMC_MTK Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> Acked-by: Yong Mao <yong.mao@mediatek.com> Link: https://lore.kernel.org/r/1595205759-5825-4-git-send-email-chun-hung.wu@mediatek.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Chun-Hung Wu
Ulf Hansson
parent
557011b6b8
commit
88bd652b3c
@ -1009,6 +1009,7 @@ config MMC_MTK
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tristate "MediaTek SD/MMC Card Interface support"
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depends on HAS_DMA
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select REGULATOR
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select MMC_CQHCI
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help
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This selects the MediaTek(R) Secure digital and Multimedia card Interface.
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If you have a machine with a integrated SD/MMC card reader, say Y or M here.
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@ -31,6 +31,8 @@
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/slot-gpio.h>
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#include "cqhci.h"
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#define MAX_BD_NUM 1024
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/*--------------------------------------------------------------------------*/
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@ -152,6 +154,7 @@
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#define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
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#define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
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#define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
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#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */
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/* MSDC_INTEN mask */
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#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
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@ -182,6 +185,7 @@
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/* SDC_CFG mask */
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#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
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#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
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#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */
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#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
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#define SDC_CFG_SDIO (0x1 << 19) /* RW */
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#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
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@ -230,6 +234,7 @@
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#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
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#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
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#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */
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#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
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#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
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@ -431,9 +436,11 @@ struct msdc_host {
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/* cmd response sample selection for HS400 */
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bool hs400_mode; /* current eMMC will run at hs400 mode */
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bool internal_cd; /* Use internal card-detect logic */
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bool cqhci; /* support eMMC hw cmdq */
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struct msdc_save_para save_para; /* used when gate HCLK */
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struct msdc_tune_para def_tune_para; /* default tune setting */
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struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
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struct cqhci_host *cq_host;
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};
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static const struct mtk_mmc_compatible mt8135_compat = {
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@ -764,6 +771,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
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(u32)(timeout > 255 ? 255 : timeout));
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}
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static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
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{
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u64 timeout;
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timeout = msdc_timeout_cal(host, ns, clks);
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sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
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(u32)(timeout > 8191 ? 8191 : timeout));
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}
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static void msdc_gate_clock(struct msdc_host *host)
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{
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clk_disable_unprepare(host->src_clk_cg);
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@ -1480,6 +1496,34 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
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pm_runtime_put_noidle(host->dev);
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}
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static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
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{
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int cmd_err = 0, dat_err = 0;
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if (intsts & MSDC_INT_RSPCRCERR) {
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cmd_err = -EILSEQ;
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dev_err(host->dev, "%s: CMD CRC ERR", __func__);
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} else if (intsts & MSDC_INT_CMDTMO) {
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cmd_err = -ETIMEDOUT;
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dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
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}
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if (intsts & MSDC_INT_DATCRCERR) {
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dat_err = -EILSEQ;
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dev_err(host->dev, "%s: DATA CRC ERR", __func__);
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} else if (intsts & MSDC_INT_DATTMO) {
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dat_err = -ETIMEDOUT;
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dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
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}
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if (cmd_err || dat_err) {
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dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
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cmd_err, dat_err, intsts);
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}
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return cqhci_irq(host->mmc, 0, cmd_err, dat_err);
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}
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static irqreturn_t msdc_irq(int irq, void *dev_id)
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{
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struct msdc_host *host = (struct msdc_host *) dev_id;
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@ -1516,6 +1560,14 @@ static irqreturn_t msdc_irq(int irq, void *dev_id)
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if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
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break;
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if ((host->mmc->caps2 & MMC_CAP2_CQE) &&
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(events & MSDC_INT_CMDQ)) {
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msdc_cmdq_irq(host, events);
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/* clear interrupts */
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writel(events, host->base + MSDC_INT);
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return IRQ_HANDLED;
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}
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if (!mrq) {
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dev_err(host->dev,
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"%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
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@ -2200,6 +2252,36 @@ static int msdc_get_cd(struct mmc_host *mmc)
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return !val;
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}
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static void msdc_cqe_enable(struct mmc_host *mmc)
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{
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struct msdc_host *host = mmc_priv(mmc);
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/* enable cmdq irq */
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writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
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/* enable busy check */
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sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
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/* default write data / busy timeout 20s */
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msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
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/* default read data timeout 1s */
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msdc_set_timeout(host, 1000000000ULL, 0);
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}
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void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
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{
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struct msdc_host *host = mmc_priv(mmc);
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/* disable cmdq irq */
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sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
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/* disable busy check */
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sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
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if (recovery) {
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sdr_set_field(host->base + MSDC_DMA_CTRL,
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MSDC_DMA_CTRL_STOP, 1);
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msdc_reset_hw(host);
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}
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}
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static const struct mmc_host_ops mt_msdc_ops = {
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.post_req = msdc_post_req,
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.pre_req = msdc_pre_req,
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@ -2216,6 +2298,11 @@ static const struct mmc_host_ops mt_msdc_ops = {
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.hw_reset = msdc_hw_reset,
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};
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static const struct cqhci_host_ops msdc_cmdq_ops = {
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.enable = msdc_cqe_enable,
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.disable = msdc_cqe_disable,
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};
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static void msdc_of_property_parse(struct platform_device *pdev,
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struct msdc_host *host)
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{
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@ -2236,6 +2323,12 @@ static void msdc_of_property_parse(struct platform_device *pdev,
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host->hs400_cmd_resp_sel_rising = true;
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else
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host->hs400_cmd_resp_sel_rising = false;
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if (of_property_read_bool(pdev->dev.of_node,
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"supports-cqe"))
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host->cqhci = true;
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else
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host->cqhci = false;
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}
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static int msdc_drv_probe(struct platform_device *pdev)
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@ -2351,6 +2444,8 @@ static int msdc_drv_probe(struct platform_device *pdev)
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mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
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mmc->caps |= MMC_CAP_CMD23;
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if (host->cqhci)
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mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
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/* MMC core transfer sizes tunable parameters */
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mmc->max_segs = MAX_BD_NUM;
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if (host->dev_comp->support_64g)
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@ -2366,6 +2461,26 @@ static int msdc_drv_probe(struct platform_device *pdev)
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host->dma_mask = DMA_BIT_MASK(32);
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mmc_dev(mmc)->dma_mask = &host->dma_mask;
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if (mmc->caps2 & MMC_CAP2_CQE) {
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host->cq_host = devm_kzalloc(host->mmc->parent,
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sizeof(*host->cq_host),
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GFP_KERNEL);
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if (!host->cq_host) {
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ret = -ENOMEM;
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goto host_free;
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}
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host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
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host->cq_host->mmio = host->base + 0x800;
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host->cq_host->ops = &msdc_cmdq_ops;
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ret = cqhci_init(host->cq_host, mmc, true);
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if (ret)
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goto host_free;
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mmc->max_segs = 128;
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/* cqhci 16bit length */
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/* 0 size, means 65536 so we don't have to -1 here */
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mmc->max_seg_size = 64 * 1024;
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}
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host->timeout_clks = 3 * 1048576;
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host->dma.gpd = dma_alloc_coherent(&pdev->dev,
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2 * sizeof(struct mt_gpdma_desc),
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