mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-27 06:30:56 +07:00
drm/nve0/fifo: single printk for mmu fault data
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
3d61b967d2
commit
885f3ced1a
@ -409,9 +409,35 @@ static const struct nouveau_enum nve0_fifo_sched_reason[] = {
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{}
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};
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static const struct nouveau_enum nve0_fifo_fault_engine[] = {
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static void
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nve0_fifo_intr_sched(struct nve0_fifo_priv *priv)
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{
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u32 intr = nv_rd32(priv, 0x00254c);
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u32 code = intr & 0x000000ff;
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nv_error(priv, "SCHED_ERROR [");
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nouveau_enum_print(nve0_fifo_sched_reason, code);
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pr_cont("]\n");
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}
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static void
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nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv)
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{
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u32 stat = nv_rd32(priv, 0x00256c);
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nv_error(priv, "CHSW_ERROR 0x%08x\n", stat);
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nv_wr32(priv, 0x00256c, stat);
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}
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static void
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nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv)
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{
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u32 stat = nv_rd32(priv, 0x00259c);
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nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat);
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}
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static const struct nouveau_enum
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nve0_fifo_fault_engine[] = {
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{ 0x00, "GR", NULL, NVDEV_ENGINE_GR },
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{ 0x03, "IFB" },
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{ 0x03, "IFB", NULL, NVDEV_ENGINE_IFB },
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{ 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
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{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
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{ 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO },
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@ -429,7 +455,8 @@ static const struct nouveau_enum nve0_fifo_fault_engine[] = {
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{}
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};
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static const struct nouveau_enum nve0_fifo_fault_reason[] = {
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static const struct nouveau_enum
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nve0_fifo_fault_reason[] = {
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{ 0x00, "PDE" },
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{ 0x01, "PDE_SIZE" },
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{ 0x02, "PTE" },
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@ -449,7 +476,8 @@ static const struct nouveau_enum nve0_fifo_fault_reason[] = {
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{}
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};
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static const struct nouveau_enum nve0_fifo_fault_hubclient[] = {
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static const struct nouveau_enum
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nve0_fifo_fault_hubclient[] = {
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{ 0x00, "VIP" },
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{ 0x01, "CE0" },
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{ 0x02, "CE1" },
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@ -485,7 +513,8 @@ static const struct nouveau_enum nve0_fifo_fault_hubclient[] = {
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{}
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};
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static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = {
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static const struct nouveau_enum
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nve0_fifo_fault_gpcclient[] = {
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{ 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
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{ 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
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{ 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
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@ -510,74 +539,68 @@ static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = {
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{}
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};
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static void
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nve0_fifo_intr_sched(struct nve0_fifo_priv *priv)
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{
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u32 intr = nv_rd32(priv, 0x00254c);
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u32 code = intr & 0x000000ff;
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nv_error(priv, "SCHED_ERROR [");
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nouveau_enum_print(nve0_fifo_sched_reason, code);
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pr_cont("]\n");
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}
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static void
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nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv)
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{
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u32 stat = nv_rd32(priv, 0x00256c);
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nv_error(priv, "CHSW_ERROR 0x%08x\n", stat);
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nv_wr32(priv, 0x00256c, stat);
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}
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static void
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nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv)
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{
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u32 stat = nv_rd32(priv, 0x00259c);
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nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat);
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}
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static void
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nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit)
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{
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u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10));
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u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10));
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u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10));
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u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10));
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u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
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u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
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u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
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u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
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u32 gpc = (stat & 0x1f000000) >> 24;
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u32 client = (stat & 0x00001f00) >> 8;
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struct nouveau_engine *engine = NULL;
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u32 write = (stat & 0x00000080);
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u32 hub = (stat & 0x00000040);
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u32 reason = (stat & 0x0000000f);
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struct nouveau_object *engctx = NULL;
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const struct nouveau_enum *en;
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const char *name = "unknown";
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struct nouveau_engine *engine;
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const struct nouveau_enum *er, *eu, *ec;
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char erunk[6] = "";
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char euunk[6] = "";
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char ecunk[6] = "";
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char gpcid[3] = "";
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nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ?
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"write" : "read", (u64)vahi << 32 | valo);
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nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
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pr_cont("] from ");
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en = nouveau_enum_print(nve0_fifo_fault_engine, unit);
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if (stat & 0x00000040) {
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pr_cont("/");
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nouveau_enum_print(nve0_fifo_fault_hubclient, client);
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} else {
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pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
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nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
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}
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er = nouveau_enum_find(nve0_fifo_fault_reason, reason);
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if (!er)
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snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
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if (en && en->data2) {
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if (en->data2 == NVDEV_SUBDEV_BAR) {
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eu = nouveau_enum_find(nve0_fifo_fault_engine, unit);
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if (eu) {
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switch (eu->data2) {
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case NVDEV_SUBDEV_BAR:
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nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
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name = "BAR1";
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} else
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if (en->data2 == NVDEV_SUBDEV_INSTMEM) {
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break;
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case NVDEV_SUBDEV_INSTMEM:
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nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
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name = "BAR3";
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} else {
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engine = nouveau_engine(priv, en->data2);
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if (engine) {
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break;
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case NVDEV_ENGINE_IFB:
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nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
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break;
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default:
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engine = nouveau_engine(priv, eu->data2);
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if (engine)
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engctx = nouveau_engctx_get(engine, inst);
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name = nouveau_client_name(engctx);
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}
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break;
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}
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} else {
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snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
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}
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pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, name);
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if (hub) {
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ec = nouveau_enum_find(nve0_fifo_fault_hubclient, client);
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} else {
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ec = nouveau_enum_find(nve0_fifo_fault_gpcclient, client);
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snprintf(gpcid, sizeof(gpcid), "%d", gpc);
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}
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if (!ec)
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snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
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nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
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"channel 0x%010llx [%s]\n", write ? "write" : "read",
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(u64)vahi << 32 | valo, er ? er->name : erunk,
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eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
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ec ? ec->name : ecunk, (u64)inst << 12,
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nouveau_client_name(engctx));
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nouveau_engctx_put(engctx);
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}
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@ -716,16 +739,13 @@ nve0_fifo_intr(struct nouveau_subdev *subdev)
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}
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if (stat & 0x10000000) {
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u32 units = nv_rd32(priv, 0x00259c);
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u32 u = units;
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while (u) {
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int i = ffs(u) - 1;
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nve0_fifo_intr_fault(priv, i);
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u &= ~(1 << i);
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u32 mask = nv_rd32(priv, 0x00259c);
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while (mask) {
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u32 unit = __ffs(mask);
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nve0_fifo_intr_fault(priv, unit);
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nv_wr32(priv, 0x00259c, (1 << unit));
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mask &= ~(1 << unit);
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}
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nv_wr32(priv, 0x00259c, units);
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stat &= ~0x10000000;
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}
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