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OMAP2PLUS: DSS2: Make members of dss_clk_source generic
The enum members of 'dss_clk_source' have clock source names specific to OMAP2/3. Change the names to more generic terms such that they now describe where the clocks come from and what they are used for. Also, change the enum member names to have "DSS_CLK_SRC" instead of "DSS_SRC" for more clarity. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -2334,7 +2334,7 @@ unsigned long dispc_fclk_rate(void)
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{
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unsigned long r = 0;
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if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
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if (dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK)
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r = dss_clk_get_rate(DSS_CLK_FCK);
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else
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#ifdef CONFIG_OMAP2_DSS_DSI
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@ -2385,7 +2385,7 @@ void dispc_dump_clocks(struct seq_file *s)
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seq_printf(s, "- DISPC -\n");
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seq_printf(s, "dispc fclk source = %s\n",
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dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
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dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
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"dss1_alwon_fclk" : "dsi1_pll_fclk");
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seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
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@ -57,7 +57,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
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if (r)
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return r;
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dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
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dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
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r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
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if (r)
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@ -217,7 +217,7 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
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dssdev->manager->disable(dssdev->manager);
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#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
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dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
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dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
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dsi_pll_uninit();
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dss_clk_disable(DSS_CLK_SYSCK);
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#endif
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@ -731,7 +731,7 @@ static unsigned long dsi_fclk_rate(void)
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{
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unsigned long r;
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if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
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if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {
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/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
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r = dss_clk_get_rate(DSS_CLK_FCK);
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} else {
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@ -1188,19 +1188,19 @@ void dsi_dump_clocks(struct seq_file *s)
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seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
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cinfo->dsi1_pll_fclk,
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cinfo->regm3,
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dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
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dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
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"off" : "on");
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seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
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cinfo->dsi2_pll_fclk,
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cinfo->regm4,
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dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
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dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
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"off" : "on");
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seq_printf(s, "- DSI -\n");
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seq_printf(s, "dsi fclk source = %s\n",
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dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
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dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
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"dss1_alwon_fclk" : "dsi2_pll_fclk");
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seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
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@ -3038,8 +3038,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
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if (r)
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goto err1;
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dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
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dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
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dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
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dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);
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DSSDBG("PLL OK\n");
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@ -3075,8 +3075,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
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err3:
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dsi_complexio_uninit();
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err2:
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dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
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dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
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dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
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dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
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err1:
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dsi_pll_uninit();
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err0:
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@ -3092,8 +3092,8 @@ static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
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dsi_vc_enable(2, 0);
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dsi_vc_enable(3, 0);
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dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
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dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
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dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
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dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
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dsi_complexio_uninit();
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dsi_pll_uninit();
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}
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@ -278,12 +278,12 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
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{
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int b;
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BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK &&
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clk_src != DSS_SRC_DSS1_ALWON_FCLK);
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BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC &&
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clk_src != DSS_CLK_SRC_FCK);
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b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
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b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
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if (clk_src == DSS_SRC_DSI1_PLL_FCLK)
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if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)
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dsi_wait_dsi1_pll_active();
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REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
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@ -295,12 +295,12 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
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{
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int b;
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BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK &&
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clk_src != DSS_SRC_DSS1_ALWON_FCLK);
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BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI &&
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clk_src != DSS_CLK_SRC_FCK);
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b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
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b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
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if (clk_src == DSS_SRC_DSI2_PLL_FCLK)
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if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)
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dsi_wait_dsi2_pll_active();
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REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
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@ -601,8 +601,8 @@ static int dss_init(bool skip_init)
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}
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}
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dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
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dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
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dss.dsi_clk_source = DSS_CLK_SRC_FCK;
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dss.dispc_clk_source = DSS_CLK_SRC_FCK;
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dss_save_context();
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@ -118,9 +118,9 @@ enum dss_clock {
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};
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enum dss_clk_source {
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DSS_SRC_DSI1_PLL_FCLK,
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DSS_SRC_DSI2_PLL_FCLK,
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DSS_SRC_DSS1_ALWON_FCLK,
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DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* DSI1_PLL_FCLK */
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DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* DSI2_PLL_FCLK */
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DSS_CLK_SRC_FCK, /* DSS1_ALWON_FCLK */
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};
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struct dss_clock_info {
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