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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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iommu/arm-smmu-v3: Add support for Substream IDs
At the moment, the SMMUv3 driver implements only one stage-1 or stage-2
page directory per device. However SMMUv3 allows more than one address
space for some devices, by providing multiple stage-1 page directories. In
addition to the Stream ID (SID), that identifies a device, we can now have
Substream IDs (SSID) identifying an address space. In PCIe, SID is called
Requester ID (RID) and SSID is called Process Address-Space ID (PASID).
A complete stage-1 walk goes through the context descriptor table:
Stream tables Ctx. Desc. tables Page tables
+--------+ ,------->+-------+ ,------->+-------+
: : | : : | : :
+--------+ | +-------+ | +-------+
SID->| STE |---' SSID->| CD |---' IOVA->| PTE |--> IPA
+--------+ +-------+ +-------+
: : : : : :
+--------+ +-------+ +-------+
Rewrite arm_smmu_write_ctx_desc() to modify context descriptor table
entries. To keep things simple we only implement one level of context
descriptor tables here, but as with stream and page tables, an SSID can
be split to index multiple levels of tables.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Jean-Philippe Brucker
Will Deacon
parent
a557aff0c7
commit
87f42391f6
@ -226,6 +226,11 @@
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#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
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#define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
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#define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0)
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#define STRTAB_STE_1_S1DSS_TERMINATE 0x0
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#define STRTAB_STE_1_S1DSS_BYPASS 0x1
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#define STRTAB_STE_1_S1DSS_SSID0 0x2
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#define STRTAB_STE_1_S1C_CACHE_NC 0UL
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#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL
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#define STRTAB_STE_1_S1C_CACHE_WT 2UL
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@ -322,6 +327,7 @@
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#define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0)
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#define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12)
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#define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12)
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#define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32)
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#define CMDQ_CFGI_1_LEAF (1UL << 0)
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#define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0)
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@ -435,8 +441,11 @@ struct arm_smmu_cmdq_ent {
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#define CMDQ_OP_CFGI_STE 0x3
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#define CMDQ_OP_CFGI_ALL 0x4
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#define CMDQ_OP_CFGI_CD 0x5
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#define CMDQ_OP_CFGI_CD_ALL 0x6
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struct {
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u32 sid;
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u32 ssid;
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union {
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bool leaf;
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u8 span;
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@ -558,6 +567,7 @@ struct arm_smmu_ctx_desc_cfg {
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struct arm_smmu_s1_cfg {
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struct arm_smmu_ctx_desc_cfg cdcfg;
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struct arm_smmu_ctx_desc cd;
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u8 s1fmt;
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u8 s1cdmax;
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};
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@ -850,10 +860,16 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
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cmd[1] |= FIELD_PREP(CMDQ_PREFETCH_1_SIZE, ent->prefetch.size);
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cmd[1] |= ent->prefetch.addr & CMDQ_PREFETCH_1_ADDR_MASK;
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break;
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case CMDQ_OP_CFGI_CD:
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cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid);
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/* Fallthrough */
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case CMDQ_OP_CFGI_STE:
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cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);
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cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf);
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break;
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case CMDQ_OP_CFGI_CD_ALL:
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cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);
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break;
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case CMDQ_OP_CFGI_ALL:
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/* Cover the entire SID range */
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cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31);
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@ -1447,34 +1463,101 @@ static int arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu)
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}
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/* Context descriptor manipulation functions */
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static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
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struct arm_smmu_s1_cfg *cfg)
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static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain,
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int ssid, bool leaf)
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{
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size_t i;
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unsigned long flags;
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struct arm_smmu_master *master;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_cmdq_ent cmd = {
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.opcode = CMDQ_OP_CFGI_CD,
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.cfgi = {
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.ssid = ssid,
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.leaf = leaf,
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},
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};
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spin_lock_irqsave(&smmu_domain->devices_lock, flags);
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list_for_each_entry(master, &smmu_domain->devices, domain_head) {
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for (i = 0; i < master->num_sids; i++) {
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cmd.cfgi.sid = master->sids[i];
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arm_smmu_cmdq_issue_cmd(smmu, &cmd);
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}
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}
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spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
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arm_smmu_cmdq_issue_sync(smmu);
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}
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static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain,
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int ssid, struct arm_smmu_ctx_desc *cd)
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{
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/*
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* This function handles the following cases:
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*
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* (1) Install primary CD, for normal DMA traffic (SSID = 0).
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* (2) Install a secondary CD, for SID+SSID traffic.
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* (3) Update ASID of a CD. Atomically write the first 64 bits of the
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* CD, then invalidate the old entry and mappings.
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* (4) Remove a secondary CD.
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*/
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u64 val;
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__le64 *cdptr = cfg->cdcfg.cdtab;
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bool cd_live;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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__le64 *cdptr = smmu_domain->s1_cfg.cdcfg.cdtab + ssid *
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CTXDESC_CD_DWORDS;
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val = le64_to_cpu(cdptr[0]);
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cd_live = !!(val & CTXDESC_CD_0_V);
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if (!cd) { /* (4) */
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val = 0;
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} else if (cd_live) { /* (3) */
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val &= ~CTXDESC_CD_0_ASID;
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val |= FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid);
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/*
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* Until CD+TLB invalidation, both ASIDs may be used for tagging
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* this substream's traffic
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*/
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} else { /* (1) and (2) */
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cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK);
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cdptr[2] = 0;
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cdptr[3] = cpu_to_le64(cd->mair);
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/*
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* STE is live, and the SMMU might read dwords of this CD in any
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* order. Ensure that it observes valid values before reading
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* V=1.
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*/
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arm_smmu_sync_cd(smmu_domain, ssid, true);
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val = cd->tcr |
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#ifdef __BIG_ENDIAN
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CTXDESC_CD_0_ENDI |
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#endif
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CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET |
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CTXDESC_CD_0_AA64 |
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FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) |
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CTXDESC_CD_0_V;
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/* STALL_MODEL==0b10 && CD.S==0 is ILLEGAL */
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if (smmu->features & ARM_SMMU_FEAT_STALL_FORCE)
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val |= CTXDESC_CD_0_S;
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}
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/*
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* We don't need to issue any invalidation here, as we'll invalidate
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* the STE when installing the new entry anyway.
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* The SMMU accesses 64-bit values atomically. See IHI0070Ca 3.21.3
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* "Configuration structures and configuration invalidation completion"
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*
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* The size of single-copy atomic reads made by the SMMU is
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* IMPLEMENTATION DEFINED but must be at least 64 bits. Any single
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* field within an aligned 64-bit span of a structure can be altered
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* without first making the structure invalid.
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*/
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val = cfg->cd.tcr |
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#ifdef __BIG_ENDIAN
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CTXDESC_CD_0_ENDI |
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#endif
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CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET |
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CTXDESC_CD_0_AA64 | FIELD_PREP(CTXDESC_CD_0_ASID, cfg->cd.asid) |
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CTXDESC_CD_0_V;
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/* STALL_MODEL==0b10 && CD.S==0 is ILLEGAL */
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if (smmu->features & ARM_SMMU_FEAT_STALL_FORCE)
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val |= CTXDESC_CD_0_S;
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cdptr[0] = cpu_to_le64(val);
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val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK;
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cdptr[1] = cpu_to_le64(val);
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cdptr[3] = cpu_to_le64(cfg->cd.mair);
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WRITE_ONCE(cdptr[0], cpu_to_le64(val));
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arm_smmu_sync_cd(smmu_domain, ssid, true);
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return 0;
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}
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static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain)
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@ -1484,6 +1567,8 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain)
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struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
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struct arm_smmu_ctx_desc_cfg *cdcfg = &cfg->cdcfg;
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cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR;
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cdcfg->num_l1_ents = 1UL << cfg->s1cdmax;
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l1size = cdcfg->num_l1_ents * (CTXDESC_CD_DWORDS << 3);
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cdcfg->cdtab = dmam_alloc_coherent(smmu->dev, l1size, &cdcfg->cdtab_dma,
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@ -1625,6 +1710,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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if (s1_cfg) {
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BUG_ON(ste_live);
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dst[1] = cpu_to_le64(
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FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) |
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FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
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FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
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FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) |
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@ -1635,7 +1721,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
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dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
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val |= (s1_cfg->cdcfg.cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) |
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FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS);
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FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) |
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FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) |
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FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt);
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}
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if (s2_cfg) {
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@ -2455,7 +2543,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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master->ats_enabled = arm_smmu_ats_supported(master);
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if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)
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arm_smmu_write_ctx_desc(smmu, &smmu_domain->s1_cfg);
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arm_smmu_write_ctx_desc(smmu_domain, 0,
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&smmu_domain->s1_cfg.cd);
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arm_smmu_install_ste_for_dev(master);
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