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drm/i915/tgl: Add Wa_22010178259:tgl

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We need to explicitly set the TLB Request Timer initial value in the
BW_BUDDY registers to 0x8 rather than relying on the hardware default.

v2: Apply missing REG_FIELD_PREP to ensure 0x8 is placed in the correct
    bits during the rmw.  (Jose)

Bspec: 52890
Bspec: 50044
Fixes: 3fa01d642f ("drm/i915/tgl: Program BW_BUDDY registers during display init")
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200219215655.2923650-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
This commit is contained in:
Matt Roper 2020-02-19 13:56:55 -08:00
parent 00de702c6c
commit 87e04f7592
2 changed files with 9 additions and 0 deletions
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8
drivers/gpu/drm/i915/display/intel_display_power.c
View File

@ -5003,6 +5003,14 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
table[i].page_mask);
intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
table[i].page_mask);
/* Wa_22010178259:tgl */
intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
BW_BUDDY_TLB_REQ_TIMER_MASK,
REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
BW_BUDDY_TLB_REQ_TIMER_MASK,
REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
}
}

1
drivers/gpu/drm/i915/i915_reg.h
View File

@ -7767,6 +7767,7 @@ enum {
#define BW_BUDDY1_CTL _MMIO(0x45140)
#define BW_BUDDY2_CTL _MMIO(0x45150)
#define BW_BUDDY_DISABLE REG_BIT(31)
#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144)
#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154)