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x86, perfcounters: read out MSR_CORE_PERF_GLOBAL_STATUS with counters disabled

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Impact: make perfcounter NMI and IRQ sequence more robust

Make __smp_perf_counter_interrupt() a bit more conservative: first disable
all counters, then read out the status. Most invocations are because there
are real events, so there's no performance impact.

Code flow gets a bit simpler as well this way.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar 2008-12-08 14:20:16 +01:00
parent 241771ef01
commit 87b9cf4623
1 changed files with 5 additions and 7 deletions
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12
arch/x86/kernel/cpu/perf_counter.c
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@ -383,18 +383,16 @@ static void __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi)
struct cpu_hw_counters *cpuc;
u64 ack, status;
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
if (!status) {
ack_APIC_irq();
return;
}
/* Disable counters globally */
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0, 0);
ack_APIC_irq();
cpuc = &per_cpu(cpu_hw_counters, cpu);
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
if (!status)
goto out;
again:
ack = status;
for_each_bit(bit, (unsigned long *) &status, nr_hw_counters) {
@ -440,7 +438,7 @@ static void __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi)
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
if (status)
goto again;
out:
/*
* Do not reenable when global enable is off:
*/