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mmc: sdhci-msm: Add CQHCI support for sdhci-msm
This adds CQHCI support for sdhci-msm platforms. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1579194192-7942-3-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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a663f64bf1
commit
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drivers/mmc/host
@ -501,6 +501,7 @@ config MMC_SDHCI_MSM
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depends on ARCH_QCOM || (ARM && COMPILE_TEST)
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depends on ARCH_QCOM || (ARM && COMPILE_TEST)
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depends on MMC_SDHCI_PLTFM
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depends on MMC_SDHCI_PLTFM
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select MMC_SDHCI_IO_ACCESSORS
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select MMC_SDHCI_IO_ACCESSORS
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select MMC_CQHCI
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help
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help
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This selects the Secure Digital Host Controller Interface (SDHCI)
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This selects the Secure Digital Host Controller Interface (SDHCI)
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support present in Qualcomm SOCs. The controller supports
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support present in Qualcomm SOCs. The controller supports
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@ -15,6 +15,7 @@
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#include <linux/regulator/consumer.h>
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#include <linux/regulator/consumer.h>
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#include "sdhci-pltfm.h"
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#include "sdhci-pltfm.h"
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#include "cqhci.h"
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#define CORE_MCI_VERSION 0x50
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#define CORE_MCI_VERSION 0x50
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#define CORE_VERSION_MAJOR_SHIFT 28
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#define CORE_VERSION_MAJOR_SHIFT 28
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@ -122,6 +123,10 @@
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#define msm_host_writel(msm_host, val, host, offset) \
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#define msm_host_writel(msm_host, val, host, offset) \
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msm_host->var_ops->msm_writel_relaxed(val, host, offset)
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msm_host->var_ops->msm_writel_relaxed(val, host, offset)
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/* CQHCI vendor specific registers */
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#define CQHCI_VENDOR_CFG1 0xA00
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#define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13)
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struct sdhci_msm_offset {
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struct sdhci_msm_offset {
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u32 core_hc_mode;
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u32 core_hc_mode;
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u32 core_mci_data_cnt;
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u32 core_mci_data_cnt;
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@ -1567,6 +1572,127 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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__sdhci_msm_set_clock(host, clock);
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__sdhci_msm_set_clock(host, clock);
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}
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}
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/*****************************************************************************\
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* *
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* MSM Command Queue Engine (CQE) *
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* *
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\*****************************************************************************/
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static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
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{
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int cmd_error = 0;
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int data_error = 0;
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if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
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return intmask;
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cqhci_irq(host->mmc, intmask, cmd_error, data_error);
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return 0;
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}
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void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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unsigned long flags;
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u32 ctrl;
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/*
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* When CQE is halted, the legacy SDHCI path operates only
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* on 16-byte descriptors in 64bit mode.
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*/
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if (host->flags & SDHCI_USE_64_BIT_DMA)
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host->desc_sz = 16;
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spin_lock_irqsave(&host->lock, flags);
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/*
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* During CQE command transfers, command complete bit gets latched.
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* So s/w should clear command complete interrupt status when CQE is
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* either halted or disabled. Otherwise unexpected SDCHI legacy
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* interrupt gets triggered when CQE is halted/disabled.
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*/
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ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
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ctrl |= SDHCI_INT_RESPONSE;
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sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
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sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
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spin_unlock_irqrestore(&host->lock, flags);
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sdhci_cqe_disable(mmc, recovery);
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}
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static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
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.enable = sdhci_cqe_enable,
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.disable = sdhci_msm_cqe_disable,
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};
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static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
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struct platform_device *pdev)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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struct cqhci_host *cq_host;
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bool dma64;
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u32 cqcfg;
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int ret;
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/*
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* When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
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* So ensure ADMA table is allocated for 16byte descriptors.
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*/
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if (host->caps & SDHCI_CAN_64BIT)
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host->alloc_desc_sz = 16;
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ret = sdhci_setup_host(host);
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if (ret)
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return ret;
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cq_host = cqhci_pltfm_init(pdev);
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if (IS_ERR(cq_host)) {
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ret = PTR_ERR(cq_host);
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dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
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goto cleanup;
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}
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msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
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cq_host->ops = &sdhci_msm_cqhci_ops;
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dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
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ret = cqhci_init(cq_host, host->mmc, dma64);
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if (ret) {
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dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
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mmc_hostname(host->mmc), ret);
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goto cleanup;
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}
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/* Disable cqe reset due to cqe enable signal */
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cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
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cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
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cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
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/*
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* SDHC expects 12byte ADMA descriptors till CQE is enabled.
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* So limit desc_sz to 12 so that the data commands that are sent
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* during card initialization (before CQE gets enabled) would
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* get executed without any issues.
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*/
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if (host->flags & SDHCI_USE_64_BIT_DMA)
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host->desc_sz = 12;
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ret = __sdhci_add_host(host);
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if (ret)
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goto cleanup;
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dev_info(&pdev->dev, "%s: CQE init: success\n",
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mmc_hostname(host->mmc));
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return ret;
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cleanup:
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sdhci_cleanup_host(host);
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return ret;
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}
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/*
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/*
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* Platform specific register write functions. This is so that, if any
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* Platform specific register write functions. This is so that, if any
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* register write needs to be followed up by platform specific actions,
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* register write needs to be followed up by platform specific actions,
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@ -1731,6 +1857,7 @@ static const struct sdhci_ops sdhci_msm_ops = {
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.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
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.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
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.write_w = sdhci_msm_writew,
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.write_w = sdhci_msm_writew,
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.write_b = sdhci_msm_writeb,
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.write_b = sdhci_msm_writeb,
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.irq = sdhci_msm_cqe_irq,
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};
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};
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static const struct sdhci_pltfm_data sdhci_msm_pdata = {
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static const struct sdhci_pltfm_data sdhci_msm_pdata = {
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@ -1753,6 +1880,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
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u8 core_major;
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u8 core_major;
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const struct sdhci_msm_offset *msm_offset;
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const struct sdhci_msm_offset *msm_offset;
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const struct sdhci_msm_variant_info *var_info;
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const struct sdhci_msm_variant_info *var_info;
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struct device_node *node = pdev->dev.of_node;
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host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
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host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
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if (IS_ERR(host))
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if (IS_ERR(host))
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@ -1948,6 +2076,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_use_autosuspend(&pdev->dev);
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host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
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host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
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if (of_property_read_bool(node, "supports-cqe"))
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ret = sdhci_msm_cqe_add_host(host, pdev);
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else
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ret = sdhci_add_host(host);
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ret = sdhci_add_host(host);
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if (ret)
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if (ret)
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goto pm_runtime_disable;
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goto pm_runtime_disable;
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