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drm/amdgpu: add gmc v9 supports for renoir
Add gfx memory controller support for renoir. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -703,6 +703,7 @@ static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
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case CHIP_VEGA10:
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case CHIP_RAVEN:
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case CHIP_ARCTURUS:
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case CHIP_RENOIR:
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return true;
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case CHIP_VEGA12:
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case CHIP_VEGA20:
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@ -1009,6 +1010,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
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adev->gmc.gart_size = 512ULL << 20;
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break;
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case CHIP_RAVEN: /* DCE SG support */
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case CHIP_RENOIR:
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adev->gmc.gart_size = 1024ULL << 20;
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break;
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}
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@ -1059,6 +1061,7 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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case CHIP_RENOIR:
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viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
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size = (REG_GET_FIELD(viewport,
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HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
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@ -1115,8 +1118,10 @@ static int gmc_v9_0_sw_init(void *handle)
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_VEGA20:
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case CHIP_RENOIR:
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adev->num_vmhubs = 2;
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/*
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* To fulfill 4-level page support,
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* vm size is 256TB (48bit), maximum size of Vega10,
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@ -1288,6 +1293,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
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case CHIP_VEGA12:
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break;
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case CHIP_RAVEN:
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/* TODO for renoir */
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soc15_program_register_sequence(adev,
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golden_settings_athub_1_0_0,
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ARRAY_SIZE(golden_settings_athub_1_0_0));
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@ -1322,6 +1328,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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/* TODO for renoir */
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mmhub_v1_0_update_power_gating(adev, true);
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break;
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default:
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