mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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x86, mrst: remove Moorestown specific serial drivers
Intel Moorestown platform support was removed few years ago. This is a follow up which removes Moorestown specific code for the serial devices. It includes mrst_max3110 and earlyprintk bits. This was used on SFI (Medfield, Clovertrail) based platforms as well, though new ones use normal serial interface for the console service. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Andy Shevchenko
Greg Kroah-Hartman
parent
934084a9d2
commit
874e52086f
@ -136,9 +136,6 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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extern struct console early_mrst_console;
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extern void mrst_early_console_init(void);
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extern struct console early_hsu_console;
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extern void hsu_early_console_init(const char *);
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@ -226,11 +226,6 @@ static int __init setup_early_printk(char *buf)
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early_console_register(&xenboot_console, keep);
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#endif
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#ifdef CONFIG_EARLY_PRINTK_INTEL_MID
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if (!strncmp(buf, "mrst", 4)) {
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mrst_early_console_init();
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early_console_register(&early_mrst_console, keep);
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}
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if (!strncmp(buf, "hsu", 3)) {
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hsu_early_console_init(buf + 3);
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early_console_register(&early_hsu_console, keep);
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@ -16,8 +16,6 @@ obj-$(subst m,y,$(CONFIG_INPUT_MPU3050)) += platform_mpu3050.o
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obj-$(subst m,y,$(CONFIG_INPUT_BMA150)) += platform_bma023.o
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obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o
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obj-$(subst m,y,$(CONFIG_DRM_MEDFIELD)) += platform_tc35876x.o
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# SPI Devices
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obj-$(subst m,y,$(CONFIG_SERIAL_MRST_MAX3110)) += platform_max3111.o
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# MISC Devices
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obj-$(subst m,y,$(CONFIG_KEYBOARD_GPIO)) += platform_gpio_keys.o
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obj-$(subst m,y,$(CONFIG_INTEL_MID_WATCHDOG)) += platform_wdt.o
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@ -1,35 +0,0 @@
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/*
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* platform_max3111.c: max3111 platform data initilization file
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*
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* (C) Copyright 2013 Intel Corporation
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* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/gpio.h>
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#include <linux/spi/spi.h>
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#include <asm/intel-mid.h>
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static void __init *max3111_platform_data(void *info)
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{
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struct spi_board_info *spi_info = info;
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int intr = get_gpio_by_name("max3111_int");
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spi_info->mode = SPI_MODE_0;
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if (intr == -1)
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return NULL;
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spi_info->irq = intr + INTEL_MID_IRQ_OFFSET;
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return NULL;
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}
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static const struct devs_id max3111_dev_id __initconst = {
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.name = "spi_max3111",
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.type = SFI_DEV_TYPE_SPI,
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.get_platform_data = &max3111_platform_data,
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};
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sfi_device(max3111_dev_id);
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@ -10,15 +10,13 @@
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*/
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/*
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* This file implements two early consoles named mrst and hsu.
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* mrst is based on Maxim3110 spi-uart device, it exists in both
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* Moorestown and Medfield platforms, while hsu is based on a High
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* Speed UART device which only exists in the Medfield platform
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* This file implements early console named hsu.
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* hsu is based on a High Speed UART device which only exists in the Medfield
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* platform
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*/
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#include <linux/serial_reg.h>
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#include <linux/serial_mfd.h>
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#include <linux/kmsg_dump.h>
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#include <linux/console.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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@ -28,216 +26,6 @@
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#include <asm/pgtable.h>
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#include <asm/intel-mid.h>
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#define MRST_SPI_TIMEOUT 0x200000
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#define MRST_REGBASE_SPI0 0xff128000
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#define MRST_REGBASE_SPI1 0xff128400
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#define MRST_CLK_SPI0_REG 0xff11d86c
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/* Bit fields in CTRLR0 */
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#define SPI_DFS_OFFSET 0
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#define SPI_FRF_OFFSET 4
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#define SPI_FRF_SPI 0x0
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#define SPI_FRF_SSP 0x1
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#define SPI_FRF_MICROWIRE 0x2
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#define SPI_FRF_RESV 0x3
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#define SPI_MODE_OFFSET 6
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#define SPI_SCPH_OFFSET 6
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#define SPI_SCOL_OFFSET 7
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#define SPI_TMOD_OFFSET 8
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#define SPI_TMOD_TR 0x0 /* xmit & recv */
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#define SPI_TMOD_TO 0x1 /* xmit only */
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#define SPI_TMOD_RO 0x2 /* recv only */
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#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
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#define SPI_SLVOE_OFFSET 10
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#define SPI_SRL_OFFSET 11
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#define SPI_CFS_OFFSET 12
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/* Bit fields in SR, 7 bits */
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#define SR_MASK 0x7f /* cover 7 bits */
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#define SR_BUSY (1 << 0)
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#define SR_TF_NOT_FULL (1 << 1)
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#define SR_TF_EMPT (1 << 2)
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#define SR_RF_NOT_EMPT (1 << 3)
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#define SR_RF_FULL (1 << 4)
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#define SR_TX_ERR (1 << 5)
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#define SR_DCOL (1 << 6)
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struct dw_spi_reg {
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u32 ctrl0;
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u32 ctrl1;
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u32 ssienr;
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u32 mwcr;
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u32 ser;
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u32 baudr;
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u32 txfltr;
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u32 rxfltr;
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u32 txflr;
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u32 rxflr;
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u32 sr;
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u32 imr;
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u32 isr;
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u32 risr;
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u32 txoicr;
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u32 rxoicr;
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u32 rxuicr;
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u32 msticr;
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u32 icr;
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u32 dmacr;
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u32 dmatdlr;
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u32 dmardlr;
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u32 idr;
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u32 version;
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/* Currently operates as 32 bits, though only the low 16 bits matter */
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u32 dr;
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} __packed;
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#define dw_readl(dw, name) __raw_readl(&(dw)->name)
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#define dw_writel(dw, name, val) __raw_writel((val), &(dw)->name)
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/* Default use SPI0 register for mrst, we will detect Penwell and use SPI1 */
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static unsigned long mrst_spi_paddr = MRST_REGBASE_SPI0;
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static u32 *pclk_spi0;
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/* Always contains an accessible address, start with 0 */
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static struct dw_spi_reg *pspi;
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static struct kmsg_dumper dw_dumper;
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static int dumper_registered;
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static void dw_kmsg_dump(struct kmsg_dumper *dumper,
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enum kmsg_dump_reason reason)
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{
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static char line[1024];
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size_t len;
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/* When run to this, we'd better re-init the HW */
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mrst_early_console_init();
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while (kmsg_dump_get_line(dumper, true, line, sizeof(line), &len))
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early_mrst_console.write(&early_mrst_console, line, len);
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}
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/* Set the ratio rate to 115200, 8n1, IRQ disabled */
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static void max3110_write_config(void)
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{
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u16 config;
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config = 0xc001;
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dw_writel(pspi, dr, config);
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}
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/* Translate char to a eligible word and send to max3110 */
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static void max3110_write_data(char c)
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{
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u16 data;
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data = 0x8000 | c;
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dw_writel(pspi, dr, data);
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}
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void mrst_early_console_init(void)
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{
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u32 ctrlr0 = 0;
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u32 spi0_cdiv;
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u32 freq; /* Freqency info only need be searched once */
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/* Base clk is 100 MHz, the actual clk = 100M / (clk_divider + 1) */
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pclk_spi0 = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
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MRST_CLK_SPI0_REG);
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spi0_cdiv = ((*pclk_spi0) & 0xe00) >> 9;
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freq = 100000000 / (spi0_cdiv + 1);
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if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL)
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mrst_spi_paddr = MRST_REGBASE_SPI1;
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pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
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mrst_spi_paddr);
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/* Disable SPI controller */
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dw_writel(pspi, ssienr, 0);
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/* Set control param, 8 bits, transmit only mode */
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ctrlr0 = dw_readl(pspi, ctrl0);
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ctrlr0 &= 0xfcc0;
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ctrlr0 |= 0xf | (SPI_FRF_SPI << SPI_FRF_OFFSET)
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dw_writel(pspi, ctrl0, ctrlr0);
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/*
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* Change the spi0 clk to comply with 115200 bps, use 100000 to
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* calculate the clk dividor to make the clock a little slower
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* than real baud rate.
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*/
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dw_writel(pspi, baudr, freq/100000);
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/* Disable all INT for early phase */
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dw_writel(pspi, imr, 0x0);
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/* Set the cs to spi-uart */
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dw_writel(pspi, ser, 0x2);
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/* Enable the HW, the last step for HW init */
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dw_writel(pspi, ssienr, 0x1);
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/* Set the default configuration */
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max3110_write_config();
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/* Register the kmsg dumper */
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if (!dumper_registered) {
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dw_dumper.dump = dw_kmsg_dump;
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kmsg_dump_register(&dw_dumper);
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dumper_registered = 1;
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}
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}
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/* Slave select should be called in the read/write function */
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static void early_mrst_spi_putc(char c)
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{
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unsigned int timeout;
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u32 sr;
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timeout = MRST_SPI_TIMEOUT;
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/* Early putc needs to make sure the TX FIFO is not full */
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while (--timeout) {
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sr = dw_readl(pspi, sr);
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if (!(sr & SR_TF_NOT_FULL))
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cpu_relax();
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else
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break;
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}
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if (!timeout)
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pr_warn("MRST earlycon: timed out\n");
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else
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max3110_write_data(c);
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}
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/* Early SPI only uses polling mode */
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static void early_mrst_spi_write(struct console *con, const char *str,
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unsigned n)
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{
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int i;
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for (i = 0; i < n && *str; i++) {
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if (*str == '\n')
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early_mrst_spi_putc('\r');
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early_mrst_spi_putc(*str);
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str++;
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}
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}
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struct console early_mrst_console = {
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.name = "earlymrst",
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.write = early_mrst_spi_write,
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.flags = CON_PRINTBUFFER,
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.index = -1,
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};
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/*
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* Following is the early console based on Medfield HSU (High
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* Speed UART) device.
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@ -259,7 +47,7 @@ void hsu_early_console_init(const char *s)
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port = clamp_val(port, 0, 2);
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paddr = HSU_PORT_BASE + port * 0x80;
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phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr);
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phsu = (void __iomem *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr);
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/* Disable FIFO */
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writeb(0x0, phsu + UART_FCR);
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@ -482,16 +482,6 @@ config SERIAL_SA1100_CONSOLE
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your boot loader (lilo or loadlin) about how to pass options to the
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kernel at boot time.)
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config SERIAL_MRST_MAX3110
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tristate "SPI UART driver for Max3110"
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depends on SPI_DW_PCI
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select SERIAL_CORE
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select SERIAL_CORE_CONSOLE
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help
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This is the UART protocol driver for the MAX3110 device on
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the Intel Moorestown platform. On other systems use the max3100
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driver.
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config SERIAL_MFD_HSU
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tristate "Medfield High Speed UART support"
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depends on PCI
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@ -77,7 +77,6 @@ obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o
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obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o
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obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o
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obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o
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obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o
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obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o
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obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o
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obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
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@ -1,909 +0,0 @@
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/*
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* mrst_max3110.c - spi uart protocol driver for Maxim 3110
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*
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* Copyright (c) 2008-2010, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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/*
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* Note:
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* 1. From Max3110 spec, the Rx FIFO has 8 words, while the Tx FIFO only has
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* 1 word. If SPI master controller doesn't support sclk frequency change,
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* then the char need be sent out one by one with some delay
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*
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* 2. Currently only RX available interrupt is used, no need for waiting TXE
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* interrupt for a low speed UART device
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#ifdef CONFIG_MAGIC_SYSRQ
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial_reg.h>
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#include <linux/kthread.h>
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#include <linux/spi/spi.h>
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#include <linux/pm.h>
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#include "mrst_max3110.h"
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#define UART_TX_NEEDED 1
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#define CON_TX_NEEDED 2
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#define BIT_IRQ_PENDING 3
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struct uart_max3110 {
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struct uart_port port;
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struct spi_device *spi;
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char name[SPI_NAME_SIZE];
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wait_queue_head_t wq;
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struct task_struct *main_thread;
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struct task_struct *read_thread;
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struct mutex thread_mutex;
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struct mutex io_mutex;
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u32 baud;
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u16 cur_conf;
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u8 clock;
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u8 parity, word_7bits;
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u16 irq;
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unsigned long uart_flags;
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/* console related */
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struct circ_buf con_xmit;
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};
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/* global data structure, may need be removed */
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static struct uart_max3110 *pmax;
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static int receive_chars(struct uart_max3110 *max,
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unsigned short *str, int len);
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static int max3110_read_multi(struct uart_max3110 *max);
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static void max3110_con_receive(struct uart_max3110 *max);
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static int max3110_write_then_read(struct uart_max3110 *max,
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const void *txbuf, void *rxbuf, unsigned len, int always_fast)
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{
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struct spi_device *spi = max->spi;
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struct spi_message message;
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struct spi_transfer x;
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int ret;
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mutex_lock(&max->io_mutex);
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spi_message_init(&message);
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memset(&x, 0, sizeof x);
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x.len = len;
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x.tx_buf = txbuf;
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x.rx_buf = rxbuf;
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spi_message_add_tail(&x, &message);
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if (always_fast)
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x.speed_hz = spi->max_speed_hz;
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else if (max->baud)
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x.speed_hz = max->baud;
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/* Do the i/o */
|
||||
ret = spi_sync(spi, &message);
|
||||
mutex_unlock(&max->io_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Write a 16b word to the device */
|
||||
static int max3110_out(struct uart_max3110 *max, const u16 out)
|
||||
{
|
||||
void *buf;
|
||||
u16 *obuf, *ibuf;
|
||||
int ret;
|
||||
|
||||
buf = kzalloc(8, GFP_KERNEL | GFP_DMA);
|
||||
if (!buf)
|
||||
return -ENOMEM;
|
||||
|
||||
obuf = buf;
|
||||
ibuf = buf + 4;
|
||||
*obuf = out;
|
||||
ret = max3110_write_then_read(max, obuf, ibuf, 2, 1);
|
||||
if (ret) {
|
||||
pr_warn("%s: get err msg %d when sending 0x%x\n",
|
||||
__func__, ret, out);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
receive_chars(max, ibuf, 1);
|
||||
|
||||
exit:
|
||||
kfree(buf);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is usually used to read data from SPIC RX FIFO, which doesn't
|
||||
* need any delay like flushing character out.
|
||||
*
|
||||
* Return how many valide bytes are read back
|
||||
*/
|
||||
static int max3110_read_multi(struct uart_max3110 *max)
|
||||
{
|
||||
void *buf;
|
||||
u16 *obuf, *ibuf;
|
||||
int ret, blen;
|
||||
|
||||
blen = M3110_RX_FIFO_DEPTH * sizeof(u16);
|
||||
buf = kzalloc(blen * 2, GFP_KERNEL | GFP_DMA);
|
||||
if (!buf)
|
||||
return 0;
|
||||
|
||||
/* tx/rx always have the same length */
|
||||
obuf = buf;
|
||||
ibuf = buf + blen;
|
||||
|
||||
if (max3110_write_then_read(max, obuf, ibuf, blen, 1)) {
|
||||
kfree(buf);
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = receive_chars(max, ibuf, M3110_RX_FIFO_DEPTH);
|
||||
|
||||
kfree(buf);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void serial_m3110_con_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
struct uart_max3110 *max =
|
||||
container_of(port, struct uart_max3110, port);
|
||||
struct circ_buf *xmit = &max->con_xmit;
|
||||
|
||||
if (uart_circ_chars_free(xmit)) {
|
||||
xmit->buf[xmit->head] = (char)ch;
|
||||
xmit->head = (xmit->head + 1) & (PAGE_SIZE - 1);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Print a string to the serial port trying not to disturb
|
||||
* any possible real use of the port...
|
||||
*
|
||||
* The console_lock must be held when we get here.
|
||||
*/
|
||||
static void serial_m3110_con_write(struct console *co,
|
||||
const char *s, unsigned int count)
|
||||
{
|
||||
if (!pmax)
|
||||
return;
|
||||
|
||||
uart_console_write(&pmax->port, s, count, serial_m3110_con_putchar);
|
||||
|
||||
if (!test_and_set_bit(CON_TX_NEEDED, &pmax->uart_flags))
|
||||
wake_up(&pmax->wq);
|
||||
}
|
||||
|
||||
static int __init
|
||||
serial_m3110_con_setup(struct console *co, char *options)
|
||||
{
|
||||
struct uart_max3110 *max = pmax;
|
||||
int baud = 115200;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
int flow = 'n';
|
||||
|
||||
pr_info("setting up console\n");
|
||||
|
||||
if (co->index == -1)
|
||||
co->index = 0;
|
||||
|
||||
if (!max) {
|
||||
pr_err("pmax is NULL, return\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
|
||||
return uart_set_options(&max->port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct tty_driver *serial_m3110_con_device(struct console *co,
|
||||
int *index)
|
||||
{
|
||||
struct uart_driver *p = co->data;
|
||||
*index = co->index;
|
||||
return p->tty_driver;
|
||||
}
|
||||
|
||||
static struct uart_driver serial_m3110_reg;
|
||||
static struct console serial_m3110_console = {
|
||||
.name = "ttyS",
|
||||
.write = serial_m3110_con_write,
|
||||
.device = serial_m3110_con_device,
|
||||
.setup = serial_m3110_con_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &serial_m3110_reg,
|
||||
};
|
||||
|
||||
static unsigned int serial_m3110_tx_empty(struct uart_port *port)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void serial_m3110_stop_tx(struct uart_port *port)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* stop_rx will be called in spin_lock env */
|
||||
static void serial_m3110_stop_rx(struct uart_port *port)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
#define WORDS_PER_XFER 128
|
||||
static void send_circ_buf(struct uart_max3110 *max,
|
||||
struct circ_buf *xmit)
|
||||
{
|
||||
void *buf;
|
||||
u16 *obuf, *ibuf;
|
||||
int i, len, blen, dma_size, left, ret = 0;
|
||||
|
||||
|
||||
dma_size = WORDS_PER_XFER * sizeof(u16) * 2;
|
||||
buf = kzalloc(dma_size, GFP_KERNEL | GFP_DMA);
|
||||
if (!buf)
|
||||
return;
|
||||
obuf = buf;
|
||||
ibuf = buf + dma_size/2;
|
||||
|
||||
while (!uart_circ_empty(xmit)) {
|
||||
left = uart_circ_chars_pending(xmit);
|
||||
while (left) {
|
||||
len = min(left, WORDS_PER_XFER);
|
||||
blen = len * sizeof(u16);
|
||||
memset(ibuf, 0, blen);
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
obuf[i] = (u8)xmit->buf[xmit->tail] | WD_TAG;
|
||||
xmit->tail = (xmit->tail + 1) &
|
||||
(UART_XMIT_SIZE - 1);
|
||||
}
|
||||
|
||||
/* Fail to send msg to console is not very critical */
|
||||
|
||||
ret = max3110_write_then_read(max, obuf, ibuf, blen, 0);
|
||||
if (ret)
|
||||
pr_warn("%s: get err msg %d\n", __func__, ret);
|
||||
|
||||
receive_chars(max, ibuf, len);
|
||||
|
||||
max->port.icount.tx += len;
|
||||
left -= len;
|
||||
}
|
||||
}
|
||||
|
||||
kfree(buf);
|
||||
}
|
||||
|
||||
static void transmit_char(struct uart_max3110 *max)
|
||||
{
|
||||
struct uart_port *port = &max->port;
|
||||
struct circ_buf *xmit = &port->state->xmit;
|
||||
|
||||
if (uart_circ_empty(xmit) || uart_tx_stopped(port))
|
||||
return;
|
||||
|
||||
send_circ_buf(max, xmit);
|
||||
|
||||
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
||||
uart_write_wakeup(port);
|
||||
|
||||
if (uart_circ_empty(xmit))
|
||||
serial_m3110_stop_tx(port);
|
||||
}
|
||||
|
||||
/*
|
||||
* This will be called by uart_write() and tty_write, can't
|
||||
* go to sleep
|
||||
*/
|
||||
static void serial_m3110_start_tx(struct uart_port *port)
|
||||
{
|
||||
struct uart_max3110 *max =
|
||||
container_of(port, struct uart_max3110, port);
|
||||
|
||||
if (!test_and_set_bit(UART_TX_NEEDED, &max->uart_flags))
|
||||
wake_up(&max->wq);
|
||||
}
|
||||
|
||||
static int
|
||||
receive_chars(struct uart_max3110 *max, unsigned short *str, int len)
|
||||
{
|
||||
struct uart_port *port = &max->port;
|
||||
struct tty_port *tport;
|
||||
char buf[M3110_RX_FIFO_DEPTH];
|
||||
int r, w, usable;
|
||||
|
||||
/* If uart is not opened, just return */
|
||||
if (!port->state)
|
||||
return 0;
|
||||
|
||||
tport = &port->state->port;
|
||||
|
||||
for (r = 0, w = 0; r < len; r++) {
|
||||
if (str[r] & MAX3110_BREAK &&
|
||||
uart_handle_break(port))
|
||||
continue;
|
||||
|
||||
if (str[r] & MAX3110_READ_DATA_AVAILABLE) {
|
||||
if (uart_handle_sysrq_char(port, str[r] & 0xff))
|
||||
continue;
|
||||
|
||||
buf[w++] = str[r] & 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
if (!w)
|
||||
return 0;
|
||||
|
||||
for (r = 0; w; r += usable, w -= usable) {
|
||||
usable = tty_buffer_request_room(tport, w);
|
||||
if (usable) {
|
||||
tty_insert_flip_string(tport, buf + r, usable);
|
||||
port->icount.rx += usable;
|
||||
}
|
||||
}
|
||||
tty_flip_buffer_push(tport);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/*
|
||||
* This routine will be used in read_thread or RX IRQ handling,
|
||||
* it will first do one round buffer read(8 words), if there is some
|
||||
* valid RX data, will try to read 5 more rounds till all data
|
||||
* is read out.
|
||||
*
|
||||
* Use stack space as data buffer to save some system load, and chose
|
||||
* 504 Btyes as a threadhold to do a bulk push to upper tty layer when
|
||||
* receiving bulk data, a much bigger buffer may cause stack overflow
|
||||
*/
|
||||
static void max3110_con_receive(struct uart_max3110 *max)
|
||||
{
|
||||
int loop = 1, num;
|
||||
|
||||
do {
|
||||
num = max3110_read_multi(max);
|
||||
|
||||
if (num) {
|
||||
loop = 5;
|
||||
}
|
||||
} while (--loop);
|
||||
}
|
||||
|
||||
static int max3110_main_thread(void *_max)
|
||||
{
|
||||
struct uart_max3110 *max = _max;
|
||||
wait_queue_head_t *wq = &max->wq;
|
||||
int ret = 0;
|
||||
struct circ_buf *xmit = &max->con_xmit;
|
||||
|
||||
pr_info("start main thread\n");
|
||||
|
||||
do {
|
||||
wait_event_interruptible(*wq,
|
||||
max->uart_flags || kthread_should_stop());
|
||||
|
||||
mutex_lock(&max->thread_mutex);
|
||||
|
||||
if (test_and_clear_bit(BIT_IRQ_PENDING, &max->uart_flags))
|
||||
max3110_con_receive(max);
|
||||
|
||||
/* first handle console output */
|
||||
if (test_and_clear_bit(CON_TX_NEEDED, &max->uart_flags))
|
||||
send_circ_buf(max, xmit);
|
||||
|
||||
/* handle uart output */
|
||||
if (test_and_clear_bit(UART_TX_NEEDED, &max->uart_flags))
|
||||
transmit_char(max);
|
||||
|
||||
mutex_unlock(&max->thread_mutex);
|
||||
|
||||
} while (!kthread_should_stop());
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static irqreturn_t serial_m3110_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct uart_max3110 *max = dev_id;
|
||||
|
||||
/* max3110's irq is a falling edge, not level triggered,
|
||||
* so no need to disable the irq */
|
||||
|
||||
if (!test_and_set_bit(BIT_IRQ_PENDING, &max->uart_flags))
|
||||
wake_up(&max->wq);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* if don't use RX IRQ, then need a thread to polling read */
|
||||
static int max3110_read_thread(void *_max)
|
||||
{
|
||||
struct uart_max3110 *max = _max;
|
||||
|
||||
pr_info("start read thread\n");
|
||||
do {
|
||||
/*
|
||||
* If can't acquire the mutex, it means the main thread
|
||||
* is running which will also perform the rx job
|
||||
*/
|
||||
if (mutex_trylock(&max->thread_mutex)) {
|
||||
max3110_con_receive(max);
|
||||
mutex_unlock(&max->thread_mutex);
|
||||
}
|
||||
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
schedule_timeout(HZ / 20);
|
||||
} while (!kthread_should_stop());
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int serial_m3110_startup(struct uart_port *port)
|
||||
{
|
||||
struct uart_max3110 *max =
|
||||
container_of(port, struct uart_max3110, port);
|
||||
u16 config = 0;
|
||||
int ret = 0;
|
||||
|
||||
if (port->line != 0) {
|
||||
pr_err("uart port startup failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Disable all IRQ and config it to 115200, 8n1 */
|
||||
config = WC_TAG | WC_FIFO_ENABLE
|
||||
| WC_1_STOPBITS
|
||||
| WC_8BIT_WORD
|
||||
| WC_BAUD_DR2;
|
||||
|
||||
/* as we use thread to handle tx/rx, need set low latency */
|
||||
port->state->port.low_latency = 1;
|
||||
|
||||
if (max->irq) {
|
||||
/* Enable RX IRQ only */
|
||||
config |= WC_RXA_IRQ_ENABLE;
|
||||
} else {
|
||||
/* If IRQ is disabled, start a read thread for input data */
|
||||
max->read_thread =
|
||||
kthread_run(max3110_read_thread, max, "max3110_read");
|
||||
if (IS_ERR(max->read_thread)) {
|
||||
ret = PTR_ERR(max->read_thread);
|
||||
max->read_thread = NULL;
|
||||
pr_err("Can't create read thread!\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = max3110_out(max, config);
|
||||
if (ret) {
|
||||
if (max->read_thread)
|
||||
kthread_stop(max->read_thread);
|
||||
max->read_thread = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
max->cur_conf = config;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void serial_m3110_shutdown(struct uart_port *port)
|
||||
{
|
||||
struct uart_max3110 *max =
|
||||
container_of(port, struct uart_max3110, port);
|
||||
u16 config;
|
||||
|
||||
if (max->read_thread) {
|
||||
kthread_stop(max->read_thread);
|
||||
max->read_thread = NULL;
|
||||
}
|
||||
|
||||
/* Disable interrupts from this port */
|
||||
config = WC_TAG | WC_SW_SHDI;
|
||||
max3110_out(max, config);
|
||||
}
|
||||
|
||||
static void serial_m3110_release_port(struct uart_port *port)
|
||||
{
|
||||
}
|
||||
|
||||
static int serial_m3110_request_port(struct uart_port *port)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void serial_m3110_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
port->type = PORT_MAX3100;
|
||||
}
|
||||
|
||||
static int
|
||||
serial_m3110_verify_port(struct uart_port *port, struct serial_struct *ser)
|
||||
{
|
||||
/* we don't want the core code to modify any port params */
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
static const char *serial_m3110_type(struct uart_port *port)
|
||||
{
|
||||
struct uart_max3110 *max =
|
||||
container_of(port, struct uart_max3110, port);
|
||||
return max->name;
|
||||
}
|
||||
|
||||
static void
|
||||
serial_m3110_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||
struct ktermios *old)
|
||||
{
|
||||
struct uart_max3110 *max =
|
||||
container_of(port, struct uart_max3110, port);
|
||||
unsigned char cval;
|
||||
unsigned int baud, parity = 0;
|
||||
int clk_div = -1;
|
||||
u16 new_conf = max->cur_conf;
|
||||
|
||||
switch (termios->c_cflag & CSIZE) {
|
||||
case CS7:
|
||||
cval = UART_LCR_WLEN7;
|
||||
new_conf |= WC_7BIT_WORD;
|
||||
break;
|
||||
default:
|
||||
/* We only support CS7 & CS8 */
|
||||
termios->c_cflag &= ~CSIZE;
|
||||
termios->c_cflag |= CS8;
|
||||
case CS8:
|
||||
cval = UART_LCR_WLEN8;
|
||||
new_conf |= WC_8BIT_WORD;
|
||||
break;
|
||||
}
|
||||
|
||||
baud = uart_get_baud_rate(port, termios, old, 0, 230400);
|
||||
|
||||
/* First calc the div for 1.8MHZ clock case */
|
||||
switch (baud) {
|
||||
case 300:
|
||||
clk_div = WC_BAUD_DR384;
|
||||
break;
|
||||
case 600:
|
||||
clk_div = WC_BAUD_DR192;
|
||||
break;
|
||||
case 1200:
|
||||
clk_div = WC_BAUD_DR96;
|
||||
break;
|
||||
case 2400:
|
||||
clk_div = WC_BAUD_DR48;
|
||||
break;
|
||||
case 4800:
|
||||
clk_div = WC_BAUD_DR24;
|
||||
break;
|
||||
case 9600:
|
||||
clk_div = WC_BAUD_DR12;
|
||||
break;
|
||||
case 19200:
|
||||
clk_div = WC_BAUD_DR6;
|
||||
break;
|
||||
case 38400:
|
||||
clk_div = WC_BAUD_DR3;
|
||||
break;
|
||||
case 57600:
|
||||
clk_div = WC_BAUD_DR2;
|
||||
break;
|
||||
case 115200:
|
||||
clk_div = WC_BAUD_DR1;
|
||||
break;
|
||||
case 230400:
|
||||
if (max->clock & MAX3110_HIGH_CLK)
|
||||
break;
|
||||
default:
|
||||
/* Pick the previous baud rate */
|
||||
baud = max->baud;
|
||||
clk_div = max->cur_conf & WC_BAUD_DIV_MASK;
|
||||
tty_termios_encode_baud_rate(termios, baud, baud);
|
||||
}
|
||||
|
||||
if (max->clock & MAX3110_HIGH_CLK) {
|
||||
clk_div += 1;
|
||||
/* High clk version max3110 doesn't support B300 */
|
||||
if (baud == 300) {
|
||||
baud = 600;
|
||||
clk_div = WC_BAUD_DR384;
|
||||
}
|
||||
if (baud == 230400)
|
||||
clk_div = WC_BAUD_DR1;
|
||||
tty_termios_encode_baud_rate(termios, baud, baud);
|
||||
}
|
||||
|
||||
new_conf = (new_conf & ~WC_BAUD_DIV_MASK) | clk_div;
|
||||
|
||||
if (unlikely(termios->c_cflag & CMSPAR))
|
||||
termios->c_cflag &= ~CMSPAR;
|
||||
|
||||
if (termios->c_cflag & CSTOPB)
|
||||
new_conf |= WC_2_STOPBITS;
|
||||
else
|
||||
new_conf &= ~WC_2_STOPBITS;
|
||||
|
||||
if (termios->c_cflag & PARENB) {
|
||||
new_conf |= WC_PARITY_ENABLE;
|
||||
parity |= UART_LCR_PARITY;
|
||||
} else
|
||||
new_conf &= ~WC_PARITY_ENABLE;
|
||||
|
||||
if (!(termios->c_cflag & PARODD))
|
||||
parity |= UART_LCR_EPAR;
|
||||
max->parity = parity;
|
||||
|
||||
uart_update_timeout(port, termios->c_cflag, baud);
|
||||
|
||||
new_conf |= WC_TAG;
|
||||
if (new_conf != max->cur_conf) {
|
||||
if (!max3110_out(max, new_conf)) {
|
||||
max->cur_conf = new_conf;
|
||||
max->baud = baud;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Don't handle hw handshaking */
|
||||
static unsigned int serial_m3110_get_mctrl(struct uart_port *port)
|
||||
{
|
||||
return TIOCM_DSR | TIOCM_CAR | TIOCM_DSR;
|
||||
}
|
||||
|
||||
static void serial_m3110_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
{
|
||||
}
|
||||
|
||||
static void serial_m3110_break_ctl(struct uart_port *port, int break_state)
|
||||
{
|
||||
}
|
||||
|
||||
static void serial_m3110_pm(struct uart_port *port, unsigned int state,
|
||||
unsigned int oldstate)
|
||||
{
|
||||
}
|
||||
|
||||
static struct uart_ops serial_m3110_ops = {
|
||||
.tx_empty = serial_m3110_tx_empty,
|
||||
.set_mctrl = serial_m3110_set_mctrl,
|
||||
.get_mctrl = serial_m3110_get_mctrl,
|
||||
.stop_tx = serial_m3110_stop_tx,
|
||||
.start_tx = serial_m3110_start_tx,
|
||||
.stop_rx = serial_m3110_stop_rx,
|
||||
.break_ctl = serial_m3110_break_ctl,
|
||||
.startup = serial_m3110_startup,
|
||||
.shutdown = serial_m3110_shutdown,
|
||||
.set_termios = serial_m3110_set_termios,
|
||||
.pm = serial_m3110_pm,
|
||||
.type = serial_m3110_type,
|
||||
.release_port = serial_m3110_release_port,
|
||||
.request_port = serial_m3110_request_port,
|
||||
.config_port = serial_m3110_config_port,
|
||||
.verify_port = serial_m3110_verify_port,
|
||||
};
|
||||
|
||||
static struct uart_driver serial_m3110_reg = {
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = "MRST serial",
|
||||
.dev_name = "ttyS",
|
||||
.major = TTY_MAJOR,
|
||||
.minor = 64,
|
||||
.nr = 1,
|
||||
.cons = &serial_m3110_console,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int serial_m3110_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_device *spi = to_spi_device(dev);
|
||||
struct uart_max3110 *max = spi_get_drvdata(spi);
|
||||
|
||||
if (max->irq > 0)
|
||||
disable_irq(max->irq);
|
||||
uart_suspend_port(&serial_m3110_reg, &max->port);
|
||||
max3110_out(max, max->cur_conf | WC_SW_SHDI);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int serial_m3110_resume(struct device *dev)
|
||||
{
|
||||
struct spi_device *spi = to_spi_device(dev);
|
||||
struct uart_max3110 *max = spi_get_drvdata(spi);
|
||||
|
||||
max3110_out(max, max->cur_conf);
|
||||
uart_resume_port(&serial_m3110_reg, &max->port);
|
||||
if (max->irq > 0)
|
||||
enable_irq(max->irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(serial_m3110_pm_ops, serial_m3110_suspend,
|
||||
serial_m3110_resume);
|
||||
#define SERIAL_M3110_PM_OPS (&serial_m3110_pm_ops)
|
||||
|
||||
#else
|
||||
#define SERIAL_M3110_PM_OPS NULL
|
||||
#endif
|
||||
|
||||
static int serial_m3110_probe(struct spi_device *spi)
|
||||
{
|
||||
struct uart_max3110 *max;
|
||||
void *buffer;
|
||||
u16 res;
|
||||
int ret = 0;
|
||||
|
||||
max = kzalloc(sizeof(*max), GFP_KERNEL);
|
||||
if (!max)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Set spi info */
|
||||
spi->bits_per_word = 16;
|
||||
max->clock = MAX3110_HIGH_CLK;
|
||||
|
||||
spi_setup(spi);
|
||||
|
||||
max->port.type = PORT_MAX3100;
|
||||
max->port.fifosize = 2; /* Only have 16b buffer */
|
||||
max->port.ops = &serial_m3110_ops;
|
||||
max->port.line = 0;
|
||||
max->port.dev = &spi->dev;
|
||||
max->port.uartclk = 115200;
|
||||
|
||||
max->spi = spi;
|
||||
strcpy(max->name, spi->modalias);
|
||||
max->irq = (u16)spi->irq;
|
||||
|
||||
mutex_init(&max->thread_mutex);
|
||||
mutex_init(&max->io_mutex);
|
||||
|
||||
max->word_7bits = 0;
|
||||
max->parity = 0;
|
||||
max->baud = 0;
|
||||
|
||||
max->cur_conf = 0;
|
||||
max->uart_flags = 0;
|
||||
|
||||
/* Check if reading configuration register returns something sane */
|
||||
|
||||
res = RC_TAG;
|
||||
ret = max3110_write_then_read(max, (u8 *)&res, (u8 *)&res, 2, 0);
|
||||
if (ret < 0 || res == 0 || res == 0xffff) {
|
||||
dev_dbg(&spi->dev, "MAX3111 deemed not present (conf reg %04x)",
|
||||
res);
|
||||
ret = -ENODEV;
|
||||
goto err_get_page;
|
||||
}
|
||||
|
||||
buffer = (void *)__get_free_page(GFP_KERNEL);
|
||||
if (!buffer) {
|
||||
ret = -ENOMEM;
|
||||
goto err_get_page;
|
||||
}
|
||||
max->con_xmit.buf = buffer;
|
||||
max->con_xmit.head = 0;
|
||||
max->con_xmit.tail = 0;
|
||||
|
||||
init_waitqueue_head(&max->wq);
|
||||
|
||||
max->main_thread = kthread_run(max3110_main_thread,
|
||||
max, "max3110_main");
|
||||
if (IS_ERR(max->main_thread)) {
|
||||
ret = PTR_ERR(max->main_thread);
|
||||
goto err_kthread;
|
||||
}
|
||||
|
||||
if (max->irq) {
|
||||
ret = request_irq(max->irq, serial_m3110_irq,
|
||||
IRQ_TYPE_EDGE_FALLING, "max3110", max);
|
||||
if (ret) {
|
||||
max->irq = 0;
|
||||
dev_warn(&spi->dev,
|
||||
"unable to allocate IRQ, will use polling method\n");
|
||||
}
|
||||
}
|
||||
|
||||
spi_set_drvdata(spi, max);
|
||||
pmax = max;
|
||||
|
||||
/* Give membase a psudo value to pass serial_core's check */
|
||||
max->port.membase = (unsigned char __iomem *)0xff110000;
|
||||
uart_add_one_port(&serial_m3110_reg, &max->port);
|
||||
|
||||
return 0;
|
||||
|
||||
err_kthread:
|
||||
free_page((unsigned long)buffer);
|
||||
err_get_page:
|
||||
kfree(max);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int serial_m3110_remove(struct spi_device *dev)
|
||||
{
|
||||
struct uart_max3110 *max = spi_get_drvdata(dev);
|
||||
|
||||
if (!max)
|
||||
return 0;
|
||||
|
||||
uart_remove_one_port(&serial_m3110_reg, &max->port);
|
||||
|
||||
free_page((unsigned long)max->con_xmit.buf);
|
||||
|
||||
if (max->irq)
|
||||
free_irq(max->irq, max);
|
||||
|
||||
if (max->main_thread)
|
||||
kthread_stop(max->main_thread);
|
||||
|
||||
kfree(max);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct spi_driver uart_max3110_driver = {
|
||||
.driver = {
|
||||
.name = "spi_max3111",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = SERIAL_M3110_PM_OPS,
|
||||
},
|
||||
.probe = serial_m3110_probe,
|
||||
.remove = serial_m3110_remove,
|
||||
};
|
||||
|
||||
static int __init serial_m3110_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret = uart_register_driver(&serial_m3110_reg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = spi_register_driver(&uart_max3110_driver);
|
||||
if (ret)
|
||||
uart_unregister_driver(&serial_m3110_reg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit serial_m3110_exit(void)
|
||||
{
|
||||
spi_unregister_driver(&uart_max3110_driver);
|
||||
uart_unregister_driver(&serial_m3110_reg);
|
||||
}
|
||||
|
||||
module_init(serial_m3110_init);
|
||||
module_exit(serial_m3110_exit);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("spi:max3110-uart");
|
||||
@ -1,61 +0,0 @@
|
||||
#ifndef _MRST_MAX3110_H
|
||||
#define _MRST_MAX3110_H
|
||||
|
||||
#define MAX3110_HIGH_CLK 0x1 /* 3.6864 MHZ */
|
||||
#define MAX3110_LOW_CLK 0x0 /* 1.8432 MHZ */
|
||||
|
||||
/* status bits for all 4 MAX3110 operate modes */
|
||||
#define MAX3110_READ_DATA_AVAILABLE (1 << 15)
|
||||
#define MAX3110_WRITE_BUF_EMPTY (1 << 14)
|
||||
#define MAX3110_BREAK (1 << 10)
|
||||
|
||||
#define WC_TAG (3 << 14)
|
||||
#define RC_TAG (1 << 14)
|
||||
#define WD_TAG (2 << 14)
|
||||
#define RD_TAG (0 << 14)
|
||||
|
||||
/* bits def for write configuration */
|
||||
#define WC_FIFO_ENABLE_MASK (1 << 13)
|
||||
#define WC_FIFO_ENABLE (0 << 13)
|
||||
|
||||
#define WC_SW_SHDI (1 << 12)
|
||||
|
||||
#define WC_IRQ_MASK (0xF << 8)
|
||||
#define WC_TXE_IRQ_ENABLE (1 << 11) /* TX empty irq */
|
||||
#define WC_RXA_IRQ_ENABLE (1 << 10) /* RX available irq */
|
||||
#define WC_PAR_HIGH_IRQ_ENABLE (1 << 9)
|
||||
#define WC_REC_ACT_IRQ_ENABLE (1 << 8)
|
||||
|
||||
#define WC_IRDA_ENABLE (1 << 7)
|
||||
|
||||
#define WC_STOPBITS_MASK (1 << 6)
|
||||
#define WC_2_STOPBITS (1 << 6)
|
||||
#define WC_1_STOPBITS (0 << 6)
|
||||
|
||||
#define WC_PARITY_ENABLE_MASK (1 << 5)
|
||||
#define WC_PARITY_ENABLE (1 << 5)
|
||||
|
||||
#define WC_WORDLEN_MASK (1 << 4)
|
||||
#define WC_7BIT_WORD (1 << 4)
|
||||
#define WC_8BIT_WORD (0 << 4)
|
||||
|
||||
#define WC_BAUD_DIV_MASK (0xF)
|
||||
#define WC_BAUD_DR1 (0x0)
|
||||
#define WC_BAUD_DR2 (0x1)
|
||||
#define WC_BAUD_DR4 (0x2)
|
||||
#define WC_BAUD_DR8 (0x3)
|
||||
#define WC_BAUD_DR16 (0x4)
|
||||
#define WC_BAUD_DR32 (0x5)
|
||||
#define WC_BAUD_DR64 (0x6)
|
||||
#define WC_BAUD_DR128 (0x7)
|
||||
#define WC_BAUD_DR3 (0x8)
|
||||
#define WC_BAUD_DR6 (0x9)
|
||||
#define WC_BAUD_DR12 (0xA)
|
||||
#define WC_BAUD_DR24 (0xB)
|
||||
#define WC_BAUD_DR48 (0xC)
|
||||
#define WC_BAUD_DR96 (0xD)
|
||||
#define WC_BAUD_DR192 (0xE)
|
||||
#define WC_BAUD_DR384 (0xF)
|
||||
|
||||
#define M3110_RX_FIFO_DEPTH 8
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user