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STM32 DT updates for v5.10, round 1

Browse Source 
Highlights:
 ----------
 
 MCU part:
  -Some changes on stm32h743: enable display controler, add SPI resets,
   use "st,stm32h7-uart" compatible.
 
 MPU part:
  -Add new Odyssey SOM board based on STM32MP157CAC. It embeds 4GB eMMC, 512
   MB DDR3 RAM, USB and ETH connectors and a combo wifi/BT (AP6236 chip).
  -Add FMC2 EBI support on EV1 board.
  -Add arm-pmu node.
  -LXA:
   -Change ethernet phy delays to avoid kernel warnings.
   -Enable DDR50 eMMC mode.
  -DH:
   -Add new DH DRC02 unit board.
   -Add USB OTG support on PDK2 board.
   -Use uart8 RTS/CTS on PDK2 board.
   -Fix display PWM channel on PDK2 board.
   -Swap phy reset line and touchscreen irq on DHCOM SOM.
   -Drop QSPI CS2 on DHCOM SOM.
   -Update SDMMC pin config on AV96.
   -Enable uart7 RTS/CTS on AV96.
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Merge tag 'stm32-dt-for-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt

STM32 DT updates for v5.10, round 1

Highlights:
----------

MCU part:
 -Some changes on stm32h743: enable display controler, add SPI resets,
  use "st,stm32h7-uart" compatible.

MPU part:
 -Add new Odyssey SOM board based on STM32MP157CAC. It embeds 4GB eMMC, 512
  MB DDR3 RAM, USB and ETH connectors and a combo wifi/BT (AP6236 chip).
 -Add FMC2 EBI support on EV1 board.
 -Add arm-pmu node.
 -LXA:
  -Change ethernet phy delays to avoid kernel warnings.
  -Enable DDR50 eMMC mode.
 -DH:
  -Add new DH DRC02 unit board.
  -Add USB OTG support on PDK2 board.
  -Use uart8 RTS/CTS on PDK2 board.
  -Fix display PWM channel on PDK2 board.
  -Swap phy reset line and touchscreen irq on DHCOM SOM.
  -Drop QSPI CS2 on DHCOM SOM.
  -Update SDMMC pin config on AV96.
  -Enable uart7 RTS/CTS on AV96.

* tag 'stm32-dt-for-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32: add arm-pmu node on stm32mp15
  ARM: dts: stm32: add FMC2 EBI support for stm32mp157c
  ARM: dts: stm32: lxa-mc1: enable DDR50 mode on eMMC
  ARM: dts: stm32: Fix DH PDK2 display PWM channel
  ARM: dts: stm32: Enable RTS/CTS for DH AV96 UART7
  ARM: dts: stm32: Swap PHY reset GPIO and TSC2004 IRQ on DHCOM SOM
  ARM: dts: stm32: use stm32h7 usart compatible string for stm32h743
  ARM: dts: stm32: add resets property to spi device nodes on stm32h743
  ARM: dts: stm32: add display controller node to stm32h743
  ARM: dts: stm32: Enable RTS/CTS for DH PDK2 UART8
  ARM: dts: stm32: Drop QSPI CS2 pinmux on DHCOM
  ARM: dts: stm32: Add STM32MP1 UART8 RTS/CTS pinmux
  ARM: dts: stm32: add initial support for stm32mp157-odyssey board
  dt-bindings: arm: stm32: document Odyssey compatible
  dt-bindings: vendor-prefixes: add Seeed Studio
  ARM: dts: stm32: lxa-mc1: Fix kernel warning about PHY delays
  ARM: dts: stm32: Add USB OTG support to DH PDK2
  ARM: dts: stm32: Fix sdmmc2 pins on AV96
  ARM: dts: stm32: Add DHSOM based DRC02 board
  ARM: dts: stm32: Move ethernet PHY into DH SoM DT

Link: https://lore.kernel.org/r/7e2a93c9-cf37-bc93-ed6e-d9cb1808b7a3@st.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-09-26 10:22:03 -07:00
commit 873c331927
17 changed files with 708 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@ -50,4 +50,10 @@ properties:
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
- description: Odyssey STM32MP1 SoM based Boards
items:
- enum:
- seeed,stm32mp157c-odyssey
- const: seeed,stm32mp157c-odyssey-som
- const: st,stm32mp157
...

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -910,6 +910,8 @@ patternProperties:
description: Schindler
"^seagate,.*":
description: Seagate Technology PLC
"^seeed,.*":
description: Seeed Technology Co., Ltd
"^seirobotics,.*":
description: Shenzhen SEI Robotics Co., Ltd
"^semtech,.*":

4
arch/arm/boot/dts/Makefile
View File

@ -1055,6 +1055,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32746g-eval.dtb \
stm32h743i-eval.dtb \
stm32h743i-disco.dtb \
stm32mp153c-dhcom-drc02.dtb \
stm32mp157a-avenger96.dtb \
stm32mp157a-dhcor-avenger96.dtb \
stm32mp157a-dk1.dtb \
@ -1064,7 +1065,8 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \
stm32mp157c-lxa-mc1.dtb
stm32mp157c-lxa-mc1.dtb \
stm32mp157c-odyssey.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \

20
arch/arm/boot/dts/stm32h743.dtsi
View File

@ -110,6 +110,7 @@ spi2: spi@40003800 {
compatible = "st,stm32h7-spi";
reg = <0x40003800 0x400>;
interrupts = <36>;
resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
clocks = <&rcc SPI2_CK>;
status = "disabled";
@ -121,12 +122,13 @@ spi3: spi@40003c00 {
compatible = "st,stm32h7-spi";
reg = <0x40003c00 0x400>;
interrupts = <51>;
resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
clocks = <&rcc SPI3_CK>;
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
compatible = "st,stm32h7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
status = "disabled";
@ -194,7 +196,7 @@ dac2: dac@2 {
};
usart1: serial@40011000 {
compatible = "st,stm32f7-uart";
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
@ -207,6 +209,7 @@ spi1: spi@40013000 {
compatible = "st,stm32h7-spi";
reg = <0x40013000 0x400>;
interrupts = <35>;
resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
clocks = <&rcc SPI1_CK>;
status = "disabled";
};
@ -217,6 +220,7 @@ spi4: spi@40013400 {
compatible = "st,stm32h7-spi";
reg = <0x40013400 0x400>;
interrupts = <84>;
resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
clocks = <&rcc SPI4_CK>;
status = "disabled";
};
@ -227,6 +231,7 @@ spi5: spi@40015000 {
compatible = "st,stm32h7-spi";
reg = <0x40015000 0x400>;
interrupts = <85>;
resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
clocks = <&rcc SPI5_CK>;
status = "disabled";
};
@ -329,6 +334,16 @@ usbotg_fs: usb@40080000 {
status = "disabled";
};
ltdc: display-controller@50001000 {
compatible = "st,stm32-ltdc";
reg = <0x50001000 0x200>;
interrupts = <88>, <89>;
resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
clocks = <&rcc LTDC_CK>;
clock-names = "lcd";
status = "disabled";
};
mdma1: dma-controller@52000000 {
compatible = "st,stm32h7-mdma";
reg = <0x52000000 0x1000>;
@ -372,6 +387,7 @@ spi6: spi@58001400 {
compatible = "st,stm32h7-spi";
reg = <0x58001400 0x400>;
interrupts = <86>;
resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
clocks = <&rcc SPI6_CK>;
status = "disabled";
};

26
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
View File

@ -1437,6 +1437,24 @@ pins {
};
};
sdmmc2_d47_pins_d: sdmmc2-d47-3 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
};
};
sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
pins {
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
<STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
};
};
sdmmc3_b4_pins_a: sdmmc3-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
@ -1700,6 +1718,14 @@ pins2 {
};
};
uart8_rtscts_pins_a: uart8rtscts-0 {
pins {
pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
<STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
bias-disable;
};
};
spi4_pins_a: spi4-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */

50
arch/arm/boot/dts/stm32mp151.dtsi
View File

@ -23,6 +23,13 @@ cpu0: cpu@0 {
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
interrupt-parent = <&intc>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@ -1302,23 +1309,38 @@ mdma1: dma-controller@58000000 {
dma-requests = <48>;
};
fmc: nand-controller@58002000 {
compatible = "st,stm32mp15-fmc2";
reg = <0x58002000 0x1000>,
<0x80000000 0x1000>,
<0x88010000 0x1000>,
<0x88020000 0x1000>,
<0x81000000 0x1000>,
<0x89010000 0x1000>,
<0x89020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
<&mdma1 20 0x10 0x12000a08 0x0 0x0>,
<&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
fmc: memory-controller@58002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "st,stm32mp1-fmc2-ebi";
reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
<4 0 0x80000000 0x10000000>; /* NAND */
nand-controller@4,0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp1-fmc2-nfc";
reg = <4 0x00000000 0x1000>,
<4 0x08010000 0x1000>,
<4 0x08020000 0x1000>,
<4 0x01000000 0x1000>,
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
status = "disabled";
};
};
qspi: spi@58003000 {

6
arch/arm/boot/dts/stm32mp153.dtsi
View File

@ -16,6 +16,12 @@ cpu1: cpu@1 {
};
};
arm-pmu {
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
soc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";

35
arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*
* DHCOM STM32MP1 variant:
* DHCM-STM32MP153C-C065-R102-F0819-SPI-E2-CAN2-RTC-I-01D2
* DHCOM PCB number: 587-200 or newer
* DRC02 PCB number: 568-100 or newer
*/
/dts-v1/;
#include "stm32mp153.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcom-som.dtsi"
#include "stm32mp15xx-dhcom-drc02.dtsi"
/ {
model = "DH electronics STM32MP153C DHCOM DRC02";
compatible = "dh,stm32mp153c-dhcom-drc02", "dh,stm32mp153c-dhcom-som",
"st,stm32mp153";
};
&m_can1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can1_pins_a>;
pinctrl-1 = <&m_can1_sleep_pins_a>;
status = "okay";
};
&m_can2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can2_pins_a>;
pinctrl-1 = <&m_can2_sleep_pins_a>;
status = "okay";
};

4
arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts
View File

@ -4,7 +4,7 @@
*
* DHCOM STM32MP1 variant:
* DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2
* DHCOR PCB number: 587-200 or newer
* DHCOM PCB number: 587-200 or newer
* PDK2 PCB number: 516-400 or newer
*/
/dts-v1/;
@ -15,7 +15,7 @@
#include "stm32mp15xx-dhcom-pdk2.dtsi"
/ {
model = "DH Electronics STM32MP157C DHCOM Premium Developer Kit (2)";
model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)";
compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som",
"st,stm32mp157";
};

16
arch/arm/boot/dts/stm32mp157c-ev1.dts
View File

@ -158,14 +158,16 @@ &fmc {
pinctrl-0 = <&fmc_pins_a>;
pinctrl-1 = <&fmc_sleep_pins_a>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-controller@4,0 {
status = "okay";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
};
};
};

3
arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
View File

@ -121,8 +121,6 @@ ethphy: ethernet-phy@3 { /* KSZ9031RN */
reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */
interrupt-parent = <&gpioa>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */
rxc-skew-ps = <1860>;
txc-skew-ps = <1860>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
micrel,force-master;
@ -214,6 +212,7 @@ &sdmmc2 {
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>;
bus-width = <8>;
mmc-ddr-3_3v;
no-1-8-v;
no-sd;
no-sdio;

276
arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi Normal file
View File

@ -0,0 +1,276 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>.
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
model = "Seeed Studio Odyssey-STM32MP157C SOM";
compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
mcuram2: mcuram2@10000000 {
compatible = "shared-dma-pool";
reg = <0x10000000 0x40000>;
no-map;
};
vdev0vring0: vdev0vring0@10040000 {
compatible = "shared-dma-pool";
reg = <0x10040000 0x1000>;
no-map;
};
vdev0vring1: vdev0vring1@10041000 {
compatible = "shared-dma-pool";
reg = <0x10041000 0x1000>;
no-map;
};
vdev0buffer: vdev0buffer@10042000 {
compatible = "shared-dma-pool";
reg = <0x10042000 0x4000>;
no-map;
};
mcuram: mcuram@30000000 {
compatible = "shared-dma-pool";
reg = <0x30000000 0x40000>;
no-map;
};
retram: retram@38000000 {
compatible = "shared-dma-pool";
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved: gpu@d4000000 {
reg = <0xd4000000 0x4000000>;
no-map;
};
};
led {
compatible = "gpio-leds";
led-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
regulators {
compatible = "st,stpmic1-regulators";
ldo1-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo6-supply = <&v3v3>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd_ddr: buck2 {
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
v3v3: buck4 {
regulator-name = "v3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
regulator-initial-mode = <0>;
};
v1v8_audio: ldo1 {
regulator-name = "v1v8_audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO1 0>;
};
v3v3_hdmi: ldo2 {
regulator-name = "v3v3_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO2 0>;
};
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
vdda: ldo5 {
regulator-name = "vdda";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO5 0>;
regulator-boot-on;
};
v1v2_hdmi: ldo6 {
regulator-name = "v1v2_hdmi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO6 0>;
};
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
regulator-over-current-protection;
};
bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge;
};
};
onkey {
compatible = "st,stpmic1-onkey";
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
interrupt-names = "onkey-falling", "onkey-rising";
power-off-time-sec = <10>;
};
watchdog {
compatible = "st,stpmic1-wdt";
status = "disabled";
};
};
};
&ipcc {
status = "okay";
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
};
&rng1 {
status = "okay";
};
&rtc {
status = "okay";
};
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>;
non-removable;
no-sd;
no-sdio;
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
status = "okay";
};

80
arch/arm/boot/dts/stm32mp157c-odyssey.dts Normal file
View File

@ -0,0 +1,80 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>.
*/
/dts-v1/;
#include "stm32mp157c-odyssey-som.dtsi"
/ {
model = "Seeed Studio Odyssey-STM32MP157C Board";
compatible = "seeed,stm32mp157c-odyssey",
"seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
assigned-clock-parents = <&rcc PLL4_P>;
assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
st,eth-clk-sel;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@7 { /* KSZ9031RN */
reg = <7>;
reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */
reset-assert-us = <10000>;
reset-deassert-us = <300>;
};
};
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-1 = <&i2c1_sleep_pins_a>;
i2c-scl-rising-time-ns = <100>;
i2c-scl-falling-time-ns = <7>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
status = "okay";
};

157
arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi Normal file
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@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&adc {
status = "disabled";
};
&dac {
status = "disabled";
};
&gpiob {
/*
* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
* GPIO line, however the STM32 UART driver assumes RX happens
* during TX anyway and that it only controls drive enable DE
* line. Hence, the RX is always enabled here.
*/
rs485-rx-en {
gpio-hog;
gpios = <8 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "rs485-rx-en";
};
};
&gpiod {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "Out1",
"Out2", "", "", "";
};
&gpioi {
gpio-line-names = "In1", "", "", "",
"", "", "", "",
"In2", "", "", "",
"", "", "", "";
/*
* NOTE: The USB Hub on the DRC02 needs a reset signal to be
* pulled high in order to be detected by the USB Controller.
* This signal should be handled by USB power sequencing in
* order to reset the Hub when USB bus is powered down, but
* so far there is no such functionality.
*/
usb-hub {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c5 { /* TP7/TP8 */
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&sdmmc3 {
/*
* On DRC02, the SoM does not have SDIO WiFi. The pins
* are used for on-board microSD slot instead.
*/
/delete-property/broken-cd;
cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
cs-gpios = <&gpioz 3 0>;
/* Use PIO for the display */
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled"; /* Enable once there is display driver */
/*
* Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
* also connected to the display board connector.
*/
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
status = "okay";
};
/*
* Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
* however the STM32MP1 pinmux cannot map them to UART4 .
*/
&uart8 { /* RS485 */
linux,rs485-enabled-at-boot-time;
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
};

45
arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
View File

@ -11,7 +11,6 @@ aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
ethernet0 = &ethernet0;
};
chosen {
@ -26,23 +25,13 @@ clk_ext_audio_codec: clock-codec {
display_bl: display-bl {
compatible = "pwm-backlight";
pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
default-brightness-level = <8>;
enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
ethernet_vio: vioregulator {
compatible = "regulator-fixed";
regulator-name = "vio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#size-cells = <0>;
@ -141,28 +130,6 @@ &cec {
status = "okay";
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rmii_pins_a>;
pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
st,eth-ref-clk-sel;
phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@1 {
reg = <1>;
};
};
};
&i2c2 { /* Header X22 */
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
@ -304,7 +271,8 @@ &usart3 {
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
uart-has-rtscts;
status = "okay";
};
@ -314,9 +282,12 @@ &usbh_ehci {
};
&usbotg_hs {
dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
dr_mode = "otg";
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
phy-names = "usb2-phy";
phys = <&usbphyc_port1 0>;
vbus-supply = <&vbus_otg>;
status = "okay";
};

42
arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
View File

@ -9,6 +9,10 @@
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
aliases {
ethernet0 = &ethernet0;
};
memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x40000000>;
@ -55,6 +59,16 @@ retram: retram@38000000 {
no-map;
};
};
ethernet_vio: vioregulator {
compatible = "regulator-fixed";
regulator-name = "vio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
};
};
&adc {
@ -94,6 +108,28 @@ &dts {
status = "okay";
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rmii_pins_a>;
pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
st,eth-ref-clk-sel;
phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@1 {
reg = <1>;
};
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
@ -249,7 +285,7 @@ touchscreen@49 {
compatible = "ti,tsc2004";
reg = <0x49>;
vio-supply = <&v3v3>;
interrupts-extended = <&gpioh 3 IRQ_TYPE_EDGE_FALLING>;
interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>;
};
eeprom@50 {
@ -285,8 +321,8 @@ &pwr_regulators {
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;

7
arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
View File

@ -295,9 +295,9 @@ &sdmmc1 {
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>;
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
bus-width = <8>;
mmc-ddr-1_8v;
no-sd;
@ -351,6 +351,7 @@ &uart7 {
label = "LS-UART0";
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_a>;
uart-has-rtscts;
status = "okay";
};