mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 14:46:46 +07:00
Merge remote branch 'tip/oprofile' into tip/perf/core
Signed-off-by: Robert Richter <robert.richter@amd.com>
This commit is contained in:
Robert Richter
commit
86d62b6fa2
18
arch/Kconfig
18
arch/Kconfig
@ -3,11 +3,9 @@
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#
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config OPROFILE
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tristate "OProfile system profiling (EXPERIMENTAL)"
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tristate "OProfile system profiling"
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depends on PROFILING
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depends on HAVE_OPROFILE
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depends on TRACING_SUPPORT
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select TRACING
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select RING_BUFFER
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select RING_BUFFER_ALLOW_SWAP
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help
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@ -17,20 +15,6 @@ config OPROFILE
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If unsure, say N.
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config OPROFILE_IBS
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bool "OProfile AMD IBS support (EXPERIMENTAL)"
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default n
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depends on OPROFILE && SMP && X86
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help
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Instruction-Based Sampling (IBS) is a new profiling
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technique that provides rich, precise program performance
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information. IBS is introduced by AMD Family10h processors
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(AMD Opteron Quad-Core processor "Barcelona") to overcome
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the limitations of conventional performance counter
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sampling.
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If unsure, say N.
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config OPROFILE_EVENT_MULTIPLEX
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bool "OProfile multiplexing support (EXPERIMENTAL)"
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default n
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@ -159,7 +159,7 @@ static int nmi_setup_mux(void)
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for_each_possible_cpu(i) {
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per_cpu(cpu_msrs, i).multiplex =
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kmalloc(multiplex_size, GFP_KERNEL);
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kzalloc(multiplex_size, GFP_KERNEL);
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if (!per_cpu(cpu_msrs, i).multiplex)
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return 0;
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}
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@ -179,7 +179,6 @@ static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
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if (counter_config[i].enabled) {
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multiplex[i].saved = -(u64)counter_config[i].count;
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} else {
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multiplex[i].addr = 0;
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multiplex[i].saved = 0;
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}
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}
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@ -189,25 +188,27 @@ static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
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static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
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{
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struct op_msr *counters = msrs->counters;
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struct op_msr *multiplex = msrs->multiplex;
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int i;
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for (i = 0; i < model->num_counters; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (multiplex[virt].addr)
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rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
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if (counters[i].addr)
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rdmsrl(counters[i].addr, multiplex[virt].saved);
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}
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}
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static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
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{
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struct op_msr *counters = msrs->counters;
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struct op_msr *multiplex = msrs->multiplex;
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int i;
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for (i = 0; i < model->num_counters; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (multiplex[virt].addr)
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wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
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if (counters[i].addr)
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wrmsrl(counters[i].addr, multiplex[virt].saved);
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}
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}
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@ -303,11 +304,11 @@ static int allocate_msrs(void)
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int i;
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for_each_possible_cpu(i) {
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per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
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per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
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GFP_KERNEL);
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if (!per_cpu(cpu_msrs, i).counters)
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return 0;
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per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
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per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
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GFP_KERNEL);
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if (!per_cpu(cpu_msrs, i).controls)
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return 0;
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@ -22,6 +22,9 @@
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#include <asm/ptrace.h>
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#include <asm/msr.h>
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#include <asm/nmi.h>
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#include <asm/apic.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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#include "op_x86_model.h"
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#include "op_counter.h"
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@ -43,15 +46,13 @@
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static unsigned long reset_value[NUM_VIRT_COUNTERS];
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#ifdef CONFIG_OPROFILE_IBS
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/* IbsFetchCtl bits/masks */
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#define IBS_FETCH_RAND_EN (1ULL<<57)
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#define IBS_FETCH_VAL (1ULL<<49)
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#define IBS_FETCH_ENABLE (1ULL<<48)
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#define IBS_FETCH_CNT_MASK 0xFFFF0000ULL
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/*IbsOpCtl bits */
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/* IbsOpCtl bits */
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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@ -59,7 +60,7 @@ static unsigned long reset_value[NUM_VIRT_COUNTERS];
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#define IBS_FETCH_SIZE 6
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#define IBS_OP_SIZE 12
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static int has_ibs; /* AMD Family10h and later */
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static u32 ibs_caps;
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struct op_ibs_config {
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unsigned long op_enabled;
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@ -71,24 +72,52 @@ struct op_ibs_config {
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};
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static struct op_ibs_config ibs_config;
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static u64 ibs_op_ctl;
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#endif
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/*
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* IBS cpuid feature detection
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*/
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#define IBS_CPUID_FEATURES 0x8000001b
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/*
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* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
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* bit 0 is used to indicate the existence of IBS.
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*/
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#define IBS_CAPS_AVAIL (1LL<<0)
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#define IBS_CAPS_RDWROPCNT (1LL<<3)
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#define IBS_CAPS_OPCNT (1LL<<4)
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/*
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* IBS randomization macros
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*/
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#define IBS_RANDOM_BITS 12
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#define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1)
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#define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5))
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static u32 get_ibs_caps(void)
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{
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u32 ibs_caps;
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unsigned int max_level;
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if (!boot_cpu_has(X86_FEATURE_IBS))
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return 0;
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/* check IBS cpuid feature flags */
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max_level = cpuid_eax(0x80000000);
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if (max_level < IBS_CPUID_FEATURES)
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return IBS_CAPS_AVAIL;
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ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
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if (!(ibs_caps & IBS_CAPS_AVAIL))
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/* cpuid flags not valid */
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return IBS_CAPS_AVAIL;
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return ibs_caps;
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}
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
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int hw_counter = op_x86_virt_to_phys(i);
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if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
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else
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msrs->multiplex[i].addr = 0;
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}
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}
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static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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@ -98,7 +127,7 @@ static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!counter_config[virt].enabled)
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if (!reset_value[virt])
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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@ -107,10 +136,6 @@ static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
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}
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}
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#else
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static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
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#endif
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/* functions for op_amd_spec */
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@ -122,18 +147,12 @@ static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
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for (i = 0; i < NUM_COUNTERS; i++) {
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if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
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else
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msrs->counters[i].addr = 0;
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}
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for (i = 0; i < NUM_CONTROLS; i++) {
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if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
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msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
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else
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msrs->controls[i].addr = 0;
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}
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op_mux_fill_in_addresses(msrs);
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}
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static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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@ -144,7 +163,8 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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/* setup reset_value */
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for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
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if (counter_config[i].enabled)
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if (counter_config[i].enabled
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&& msrs->counters[op_x86_virt_to_phys(i)].addr)
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reset_value[i] = counter_config[i].count;
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else
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reset_value[i] = 0;
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@ -152,9 +172,18 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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/* clear all counters */
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for (i = 0; i < NUM_CONTROLS; ++i) {
|
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if (unlikely(!msrs->controls[i].addr))
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if (unlikely(!msrs->controls[i].addr)) {
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if (counter_config[i].enabled && !smp_processor_id())
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/*
|
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* counter is reserved, this is on all
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* cpus, so report only for cpu #0
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*/
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op_x86_warn_reserved(i);
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continue;
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}
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rdmsrl(msrs->controls[i].addr, val);
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if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
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op_x86_warn_in_use(i);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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}
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@ -169,9 +198,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
|
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int virt = op_x86_phys_to_virt(i);
|
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if (!counter_config[virt].enabled)
|
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continue;
|
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if (!msrs->counters[i].addr)
|
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if (!reset_value[virt])
|
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continue;
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|
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/* setup counter registers */
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@ -185,7 +212,60 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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}
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}
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|
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#ifdef CONFIG_OPROFILE_IBS
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/*
|
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* 16-bit Linear Feedback Shift Register (LFSR)
|
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*
|
||||
* 16 14 13 11
|
||||
* Feedback polynomial = X + X + X + X + 1
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*/
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static unsigned int lfsr_random(void)
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{
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static unsigned int lfsr_value = 0xF00D;
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unsigned int bit;
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|
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/* Compute next bit to shift in */
|
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bit = ((lfsr_value >> 0) ^
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(lfsr_value >> 2) ^
|
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(lfsr_value >> 3) ^
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(lfsr_value >> 5)) & 0x0001;
|
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|
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/* Advance to next register value */
|
||||
lfsr_value = (lfsr_value >> 1) | (bit << 15);
|
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|
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return lfsr_value;
|
||||
}
|
||||
|
||||
/*
|
||||
* IBS software randomization
|
||||
*
|
||||
* The IBS periodic op counter is randomized in software. The lower 12
|
||||
* bits of the 20 bit counter are randomized. IbsOpCurCnt is
|
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* initialized with a 12 bit random value.
|
||||
*/
|
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static inline u64 op_amd_randomize_ibs_op(u64 val)
|
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{
|
||||
unsigned int random = lfsr_random();
|
||||
|
||||
if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
|
||||
/*
|
||||
* Work around if the hw can not write to IbsOpCurCnt
|
||||
*
|
||||
* Randomize the lower 8 bits of the 16 bit
|
||||
* IbsOpMaxCnt [15:0] value in the range of -128 to
|
||||
* +127 by adding/subtracting an offset to the
|
||||
* maximum count (IbsOpMaxCnt).
|
||||
*
|
||||
* To avoid over or underflows and protect upper bits
|
||||
* starting at bit 16, the initial value for
|
||||
* IbsOpMaxCnt must fit in the range from 0x0081 to
|
||||
* 0xff80.
|
||||
*/
|
||||
val += (s8)(random >> 4);
|
||||
else
|
||||
val |= (u64)(random & IBS_RANDOM_MASK) << 32;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void
|
||||
op_amd_handle_ibs(struct pt_regs * const regs,
|
||||
@ -194,7 +274,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
|
||||
u64 val, ctl;
|
||||
struct op_entry entry;
|
||||
|
||||
if (!has_ibs)
|
||||
if (!ibs_caps)
|
||||
return;
|
||||
|
||||
if (ibs_config.fetch_enabled) {
|
||||
@ -236,8 +316,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
|
||||
oprofile_write_commit(&entry);
|
||||
|
||||
/* reenable the IRQ */
|
||||
ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
|
||||
ctl |= IBS_OP_ENABLE;
|
||||
ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
|
||||
wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
|
||||
}
|
||||
}
|
||||
@ -246,41 +325,57 @@ op_amd_handle_ibs(struct pt_regs * const regs,
|
||||
static inline void op_amd_start_ibs(void)
|
||||
{
|
||||
u64 val;
|
||||
if (has_ibs && ibs_config.fetch_enabled) {
|
||||
|
||||
if (!ibs_caps)
|
||||
return;
|
||||
|
||||
if (ibs_config.fetch_enabled) {
|
||||
val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
|
||||
val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
|
||||
val |= IBS_FETCH_ENABLE;
|
||||
wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
|
||||
}
|
||||
|
||||
if (has_ibs && ibs_config.op_enabled) {
|
||||
val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
|
||||
val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
|
||||
val |= IBS_OP_ENABLE;
|
||||
if (ibs_config.op_enabled) {
|
||||
ibs_op_ctl = ibs_config.max_cnt_op >> 4;
|
||||
if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
|
||||
/*
|
||||
* IbsOpCurCnt not supported. See
|
||||
* op_amd_randomize_ibs_op() for details.
|
||||
*/
|
||||
ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
|
||||
} else {
|
||||
/*
|
||||
* The start value is randomized with a
|
||||
* positive offset, we need to compensate it
|
||||
* with the half of the randomized range. Also
|
||||
* avoid underflows.
|
||||
*/
|
||||
ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
|
||||
0xFFFFULL);
|
||||
}
|
||||
if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
|
||||
ibs_op_ctl |= IBS_OP_CNT_CTL;
|
||||
ibs_op_ctl |= IBS_OP_ENABLE;
|
||||
val = op_amd_randomize_ibs_op(ibs_op_ctl);
|
||||
wrmsrl(MSR_AMD64_IBSOPCTL, val);
|
||||
}
|
||||
}
|
||||
|
||||
static void op_amd_stop_ibs(void)
|
||||
{
|
||||
if (has_ibs && ibs_config.fetch_enabled)
|
||||
if (!ibs_caps)
|
||||
return;
|
||||
|
||||
if (ibs_config.fetch_enabled)
|
||||
/* clear max count and enable */
|
||||
wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
|
||||
|
||||
if (has_ibs && ibs_config.op_enabled)
|
||||
if (ibs_config.op_enabled)
|
||||
/* clear max count and enable */
|
||||
wrmsrl(MSR_AMD64_IBSOPCTL, 0);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void op_amd_handle_ibs(struct pt_regs * const regs,
|
||||
struct op_msrs const * const msrs) { }
|
||||
static inline void op_amd_start_ibs(void) { }
|
||||
static inline void op_amd_stop_ibs(void) { }
|
||||
|
||||
#endif
|
||||
|
||||
static int op_amd_check_ctrs(struct pt_regs * const regs,
|
||||
struct op_msrs const * const msrs)
|
||||
{
|
||||
@ -355,8 +450,6 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OPROFILE_IBS
|
||||
|
||||
static u8 ibs_eilvt_off;
|
||||
|
||||
static inline void apic_init_ibs_nmi_per_cpu(void *arg)
|
||||
@ -405,45 +498,36 @@ static int init_ibs_nmi(void)
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NUMA
|
||||
/* Sanity check */
|
||||
/* Works only for 64bit with proper numa implementation. */
|
||||
if (nodes != num_possible_nodes()) {
|
||||
printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
|
||||
"found: %d, expected %d",
|
||||
nodes, num_possible_nodes());
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* uninitialize the APIC for the IBS interrupts if needed */
|
||||
static void clear_ibs_nmi(void)
|
||||
{
|
||||
if (has_ibs)
|
||||
if (ibs_caps)
|
||||
on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
|
||||
}
|
||||
|
||||
/* initialize the APIC for the IBS interrupts if available */
|
||||
static void ibs_init(void)
|
||||
{
|
||||
has_ibs = boot_cpu_has(X86_FEATURE_IBS);
|
||||
ibs_caps = get_ibs_caps();
|
||||
|
||||
if (!has_ibs)
|
||||
if (!ibs_caps)
|
||||
return;
|
||||
|
||||
if (init_ibs_nmi()) {
|
||||
has_ibs = 0;
|
||||
ibs_caps = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "oprofile: AMD IBS detected\n");
|
||||
printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
|
||||
(unsigned)ibs_caps);
|
||||
}
|
||||
|
||||
static void ibs_exit(void)
|
||||
{
|
||||
if (!has_ibs)
|
||||
if (!ibs_caps)
|
||||
return;
|
||||
|
||||
clear_ibs_nmi();
|
||||
@ -463,7 +547,7 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!has_ibs)
|
||||
if (!ibs_caps)
|
||||
return ret;
|
||||
|
||||
/* model specific files */
|
||||
@ -473,7 +557,7 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
|
||||
ibs_config.fetch_enabled = 0;
|
||||
ibs_config.max_cnt_op = 250000;
|
||||
ibs_config.op_enabled = 0;
|
||||
ibs_config.dispatched_ops = 1;
|
||||
ibs_config.dispatched_ops = 0;
|
||||
|
||||
dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
|
||||
oprofilefs_create_ulong(sb, dir, "enable",
|
||||
@ -488,8 +572,9 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
|
||||
&ibs_config.op_enabled);
|
||||
oprofilefs_create_ulong(sb, dir, "max_count",
|
||||
&ibs_config.max_cnt_op);
|
||||
oprofilefs_create_ulong(sb, dir, "dispatched_ops",
|
||||
&ibs_config.dispatched_ops);
|
||||
if (ibs_caps & IBS_CAPS_OPCNT)
|
||||
oprofilefs_create_ulong(sb, dir, "dispatched_ops",
|
||||
&ibs_config.dispatched_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -507,19 +592,6 @@ static void op_amd_exit(void)
|
||||
ibs_exit();
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
/* no IBS support */
|
||||
|
||||
static int op_amd_init(struct oprofile_operations *ops)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void op_amd_exit(void) {}
|
||||
|
||||
#endif /* CONFIG_OPROFILE_IBS */
|
||||
|
||||
struct op_x86_model_spec op_amd_spec = {
|
||||
.num_counters = NUM_COUNTERS,
|
||||
.num_controls = NUM_CONTROLS,
|
||||
|
||||
@ -394,12 +394,6 @@ static void p4_fill_in_addresses(struct op_msrs * const msrs)
|
||||
setup_num_counters();
|
||||
stag = get_stagger();
|
||||
|
||||
/* initialize some registers */
|
||||
for (i = 0; i < num_counters; ++i)
|
||||
msrs->counters[i].addr = 0;
|
||||
for (i = 0; i < num_controls; ++i)
|
||||
msrs->controls[i].addr = 0;
|
||||
|
||||
/* the counter & cccr registers we pay attention to */
|
||||
for (i = 0; i < num_counters; ++i) {
|
||||
addr = p4_counters[VIRT_CTR(stag, i)].counter_address;
|
||||
|
||||
@ -37,15 +37,11 @@ static void ppro_fill_in_addresses(struct op_msrs * const msrs)
|
||||
for (i = 0; i < num_counters; i++) {
|
||||
if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
|
||||
msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
|
||||
else
|
||||
msrs->counters[i].addr = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_counters; i++) {
|
||||
if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
|
||||
msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
|
||||
else
|
||||
msrs->controls[i].addr = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@ -57,7 +53,7 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
|
||||
int i;
|
||||
|
||||
if (!reset_value) {
|
||||
reset_value = kmalloc(sizeof(reset_value[0]) * num_counters,
|
||||
reset_value = kzalloc(sizeof(reset_value[0]) * num_counters,
|
||||
GFP_ATOMIC);
|
||||
if (!reset_value)
|
||||
return;
|
||||
@ -82,9 +78,18 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
|
||||
|
||||
/* clear all counters */
|
||||
for (i = 0; i < num_counters; ++i) {
|
||||
if (unlikely(!msrs->controls[i].addr))
|
||||
if (unlikely(!msrs->controls[i].addr)) {
|
||||
if (counter_config[i].enabled && !smp_processor_id())
|
||||
/*
|
||||
* counter is reserved, this is on all
|
||||
* cpus, so report only for cpu #0
|
||||
*/
|
||||
op_x86_warn_reserved(i);
|
||||
continue;
|
||||
}
|
||||
rdmsrl(msrs->controls[i].addr, val);
|
||||
if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
|
||||
op_x86_warn_in_use(i);
|
||||
val &= model->reserved;
|
||||
wrmsrl(msrs->controls[i].addr, val);
|
||||
}
|
||||
|
||||
@ -57,6 +57,26 @@ struct op_x86_model_spec {
|
||||
|
||||
struct op_counter_config;
|
||||
|
||||
static inline void op_x86_warn_in_use(int counter)
|
||||
{
|
||||
/*
|
||||
* The warning indicates an already running counter. If
|
||||
* oprofile doesn't collect data, then try using a different
|
||||
* performance counter on your platform to monitor the desired
|
||||
* event. Delete counter #%d from the desired event by editing
|
||||
* the /usr/share/oprofile/%s/<cpu>/events file. If the event
|
||||
* cannot be monitored by any other counter, contact your
|
||||
* hardware or BIOS vendor.
|
||||
*/
|
||||
pr_warning("oprofile: counter #%d on cpu #%d may already be used\n",
|
||||
counter, smp_processor_id());
|
||||
}
|
||||
|
||||
static inline void op_x86_warn_reserved(int counter)
|
||||
{
|
||||
pr_warning("oprofile: counter #%d is already reserved\n", counter);
|
||||
}
|
||||
|
||||
extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
|
||||
struct op_counter_config *counter_config);
|
||||
extern int op_x86_phys_to_virt(int phys);
|
||||
|
||||
@ -1099,7 +1099,7 @@ config MMAP_ALLOW_UNINITIALIZED
|
||||
See Documentation/nommu-mmap.txt for more information.
|
||||
|
||||
config PROFILING
|
||||
bool "Profiling support (EXPERIMENTAL)"
|
||||
bool "Profiling support"
|
||||
help
|
||||
Say Y here to enable the extended profiling support mechanisms used
|
||||
by profilers such as OProfile.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user