AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-24 15:20:58 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

hwmon: (hwmon-vid) Fix multi-line comments

Browse Source 
Acked-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
This commit is contained in:
Guenter Roeck 2012-01-19 11:02:18 -08:00 committed by Guenter Roeck
parent 5ed04880a3
commit 86d566e58e
1 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/hwmon/hwmon-vid.c
View File

@ -40,7 +40,7 @@
* available at http://developer.intel.com/. * available at http://developer.intel.com/.
* *
* AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094, * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
* http://support.amd.com/us/Processor_TechDocs/26094.PDF * http://support.amd.com/us/Processor_TechDocs/26094.PDF
* Table 74. VID Code Voltages * Table 74. VID Code Voltages
* This corresponds to an arbitrary VRM code of 24 in the functions below. * This corresponds to an arbitrary VRM code of 24 in the functions below.
* These CPU models (K8 revision <= E) have 5 VID pins. See also: * These CPU models (K8 revision <= E) have 5 VID pins. See also:
@ -185,10 +185,12 @@ struct vrm_model {
static struct vrm_model vrm_models[] = { static struct vrm_model vrm_models[] = {
{X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */ {X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */
{X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */ {X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
/* In theory, all NPT family 0Fh processors have 6 VID pins and should /*
thus use vrm 25, however in practice not all mainboards route the * In theory, all NPT family 0Fh processors have 6 VID pins and should
6th VID pin because it is never needed. So we use the 5 VID pin * thus use vrm 25, however in practice not all mainboards route the
variant (vrm 24) for the models which exist today. */ * 6th VID pin because it is never needed. So we use the 5 VID pin
* variant (vrm 24) for the models which exist today.
*/
{X86_VENDOR_AMD, 0xF, 0x7F, ANY, 24}, /* NPT family 0Fh */ {X86_VENDOR_AMD, 0xF, 0x7F, ANY, 24}, /* NPT family 0Fh */
{X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* future fam. 0Fh */ {X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* future fam. 0Fh */
{X86_VENDOR_AMD, 0x10, ANY, ANY, 25}, /* NPT family 10h */ {X86_VENDOR_AMD, 0x10, ANY, ANY, 25}, /* NPT family 10h */