mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
drm/i915/fbc: Allow on unfenced surfaces, for recent gen
Only fbc1 is tied to using a fence. Later iterations of fbc are more flexible and allow operation on unfenced frontbuffers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: "Zanoni, Paulo R" <paulo.r.zanoni@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20160819155428.1670-3-chris@chris-wilson.co.uk
This commit is contained in:
parent
12ecf4b979
commit
8678fdaf39
@ -799,8 +799,10 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
|
|||||||
*/
|
*/
|
||||||
if (cache->fb.tiling_mode != I915_TILING_X ||
|
if (cache->fb.tiling_mode != I915_TILING_X ||
|
||||||
cache->fb.fence_reg == I915_FENCE_REG_NONE) {
|
cache->fb.fence_reg == I915_FENCE_REG_NONE) {
|
||||||
fbc->no_fbc_reason = "framebuffer not tiled or fenced";
|
if (INTEL_GEN(dev_priv) < 5) {
|
||||||
return false;
|
fbc->no_fbc_reason = "framebuffer not tiled or fenced";
|
||||||
|
return false;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
|
if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
|
||||||
cache->plane.rotation != DRM_ROTATE_0) {
|
cache->plane.rotation != DRM_ROTATE_0) {
|
||||||
|
Loading…
Reference in New Issue
Block a user