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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-27 00:19:18 +07:00
drm/i915: Sanitize the shared DPLL reserve/release interface
For consistency s/intel_get_shared_dpll()/intel_reserve_shared_dplls()/ to better match intel_release_shared_dplls(). Also, pass to the reserve/release and get_dplls/put_dplls hooks the intel_atomic_state and CRTC object, that way these functions can look up the old or new state as needed. Also release the PLLs from the atomic state via a new put_dplls->intel_unreference_shared_dpll() call chain for better symmetry with the reservation via the get_dplls->intel_reference_shared_dpll() call chain. Since nothing uses the PLL returned by intel_reserve_shared_dplls(), make it return only a bool. While at it also clarify the reserve/release function docbook headers making it clear that multiple DPLLs will be reserved/released and whether the new or old atomic CRTC state is affected. This refactoring is also a preparation for a follow-up change that needs to reserve multiple DPLLs. Kudos to Ville for the idea to pass intel_atomic_state around, to make things clearer locally where an object's old/new atomic state is required. No functional changes. v2: - Fix checkpatch issue: typo in code comment. v3: - Rebase on drm-tip. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190628143635.22066-17-imre.deak@intel.com
This commit is contained in:
Imre Deak
parent
4f36afb26c
commit
866955fa45
@ -9493,6 +9493,8 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_atomic_state *state =
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to_intel_atomic_state(crtc_state->base.state);
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const struct intel_limit *limit;
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int refclk = 120000;
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@ -9534,7 +9536,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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ironlake_compute_dpll(crtc, crtc_state, NULL);
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if (!intel_get_shared_dpll(crtc_state, NULL)) {
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if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
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DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
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pipe_name(crtc->pipe));
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return -EINVAL;
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@ -9915,7 +9917,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_encoder *encoder =
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intel_get_crtc_new_encoder(state, crtc_state);
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if (!intel_get_shared_dpll(crtc_state, encoder)) {
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if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
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DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
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pipe_name(crtc->pipe));
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return -EINVAL;
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@ -13171,27 +13173,20 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
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static void intel_modeset_clear_plls(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_crtc_state *old_crtc_state, *new_crtc_state;
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struct intel_crtc_state *new_crtc_state;
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struct intel_crtc *crtc;
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int i;
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if (!dev_priv->display.crtc_compute_clock)
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return;
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for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
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new_crtc_state, i) {
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struct intel_shared_dpll *old_dpll =
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old_crtc_state->shared_dpll;
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for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
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if (!needs_modeset(new_crtc_state))
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continue;
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new_crtc_state->shared_dpll = NULL;
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if (!old_dpll)
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continue;
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intel_release_shared_dpll(old_dpll, crtc, &state->base);
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intel_release_shared_dplls(state, crtc);
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}
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}
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@ -36,9 +36,10 @@
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* This file provides an abstraction over display PLLs. The function
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* intel_shared_dpll_init() initializes the PLLs for the given platform. The
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* users of a PLL are tracked and that tracking is integrated with the atomic
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* modest interface. During an atomic operation, a PLL can be requested for a
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* given CRTC and encoder configuration by calling intel_get_shared_dpll() and
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* a previously used PLL can be released with intel_release_shared_dpll().
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* modset interface. During an atomic operation, required PLLs can be reserved
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* for a given CRTC and encoder configuration by calling
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* intel_reserve_shared_dplls() and previously reserved PLLs can be released
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* with intel_release_shared_dplls().
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* Changes to the users are first staged in the atomic state, and then made
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* effective by calling intel_shared_dpll_swap_state() during the atomic
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* commit phase.
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@ -309,6 +310,28 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
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shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
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}
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static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
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const struct intel_crtc *crtc,
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const struct intel_shared_dpll *pll)
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{
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struct intel_shared_dpll_state *shared_dpll;
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shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
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shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe);
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}
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static void intel_put_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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if (!crtc_state->shared_dpll)
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return;
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intel_unreference_shared_dpll(state, crtc, crtc_state->shared_dpll);
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}
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/**
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* intel_shared_dpll_swap_state - make atomic DPLL configuration effective
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* @state: atomic state
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@ -421,11 +444,12 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
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udelay(200);
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}
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static struct intel_shared_dpll *
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ibx_get_dpll(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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static bool ibx_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_encoder *encoder)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_shared_dpll *pll;
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enum intel_dpll_id i;
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@ -445,12 +469,12 @@ ibx_get_dpll(struct intel_crtc_state *crtc_state,
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}
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if (!pll)
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return NULL;
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return false;
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/* reference the pll */
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intel_reference_shared_dpll(pll, crtc_state);
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return pll;
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return true;
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}
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static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
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@ -821,10 +845,12 @@ hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)
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return pll;
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}
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static struct intel_shared_dpll *
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hsw_get_dpll(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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static bool hsw_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_encoder *encoder)
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{
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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struct intel_shared_dpll *pll;
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memset(&crtc_state->dpll_hw_state, 0,
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@ -836,7 +862,7 @@ hsw_get_dpll(struct intel_crtc_state *crtc_state,
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pll = hsw_ddi_dp_get_dpll(crtc_state);
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} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
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if (WARN_ON(crtc_state->port_clock / 2 != 135000))
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return NULL;
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return false;
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crtc_state->dpll_hw_state.spll =
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SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
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@ -844,15 +870,15 @@ hsw_get_dpll(struct intel_crtc_state *crtc_state,
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pll = intel_find_shared_dpll(crtc_state,
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DPLL_ID_SPLL, DPLL_ID_SPLL);
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} else {
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return NULL;
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return false;
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}
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if (!pll)
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return NULL;
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return false;
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intel_reference_shared_dpll(pll, crtc_state);
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return pll;
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return true;
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}
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static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
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@ -1385,10 +1411,12 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
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return true;
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}
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static struct intel_shared_dpll *
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skl_get_dpll(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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static bool skl_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_encoder *encoder)
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{
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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struct intel_shared_dpll *pll;
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bool bret;
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@ -1396,16 +1424,16 @@ skl_get_dpll(struct intel_crtc_state *crtc_state,
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bret = skl_ddi_hdmi_pll_dividers(crtc_state);
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if (!bret) {
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DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
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return NULL;
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return false;
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}
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} else if (intel_crtc_has_dp_encoder(crtc_state)) {
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bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
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if (!bret) {
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DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
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return NULL;
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return false;
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}
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} else {
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return NULL;
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return false;
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}
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
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@ -1417,11 +1445,11 @@ skl_get_dpll(struct intel_crtc_state *crtc_state,
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DPLL_ID_SKL_DPLL1,
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DPLL_ID_SKL_DPLL3);
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if (!pll)
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return NULL;
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return false;
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intel_reference_shared_dpll(pll, crtc_state);
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return pll;
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return true;
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}
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static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
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@ -1827,22 +1855,23 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
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return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
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}
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static struct intel_shared_dpll *
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bxt_get_dpll(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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static bool bxt_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_encoder *encoder)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_shared_dpll *pll;
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enum intel_dpll_id id;
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
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!bxt_ddi_hdmi_set_dpll_hw_state(crtc_state))
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return NULL;
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return false;
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if (intel_crtc_has_dp_encoder(crtc_state) &&
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!bxt_ddi_dp_set_dpll_hw_state(crtc_state))
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return NULL;
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return false;
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/* 1:1 mapping between ports and PLLs */
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id = (enum intel_dpll_id) encoder->port;
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@ -1853,7 +1882,7 @@ bxt_get_dpll(struct intel_crtc_state *crtc_state,
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intel_reference_shared_dpll(pll, crtc_state);
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return pll;
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return true;
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}
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static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
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@ -1884,8 +1913,11 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
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struct intel_dpll_mgr {
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const struct dpll_info *dpll_info;
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struct intel_shared_dpll *(*get_dpll)(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder);
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bool (*get_dplls)(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_encoder *encoder);
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void (*put_dplls)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void (*dump_hw_state)(struct drm_i915_private *dev_priv,
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const struct intel_dpll_hw_state *hw_state);
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@ -1899,7 +1931,8 @@ static const struct dpll_info pch_plls[] = {
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static const struct intel_dpll_mgr pch_pll_mgr = {
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.dpll_info = pch_plls,
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.get_dpll = ibx_get_dpll,
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.get_dplls = ibx_get_dpll,
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.put_dplls = intel_put_dpll,
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.dump_hw_state = ibx_dump_hw_state,
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};
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@ -1915,7 +1948,8 @@ static const struct dpll_info hsw_plls[] = {
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static const struct intel_dpll_mgr hsw_pll_mgr = {
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.dpll_info = hsw_plls,
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.get_dpll = hsw_get_dpll,
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.get_dplls = hsw_get_dpll,
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.put_dplls = intel_put_dpll,
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.dump_hw_state = hsw_dump_hw_state,
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};
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@ -1929,7 +1963,8 @@ static const struct dpll_info skl_plls[] = {
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static const struct intel_dpll_mgr skl_pll_mgr = {
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.dpll_info = skl_plls,
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.get_dpll = skl_get_dpll,
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.get_dplls = skl_get_dpll,
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.put_dplls = intel_put_dpll,
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.dump_hw_state = skl_dump_hw_state,
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};
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@ -1942,7 +1977,8 @@ static const struct dpll_info bxt_plls[] = {
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static const struct intel_dpll_mgr bxt_pll_mgr = {
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.dpll_info = bxt_plls,
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.get_dpll = bxt_get_dpll,
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.get_dplls = bxt_get_dpll,
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.put_dplls = intel_put_dpll,
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.dump_hw_state = bxt_dump_hw_state,
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};
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@ -2332,10 +2368,12 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
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return true;
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}
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static struct intel_shared_dpll *
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cnl_get_dpll(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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static bool cnl_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_encoder *encoder)
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{
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struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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struct intel_shared_dpll *pll;
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bool bret;
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@ -2343,18 +2381,18 @@ cnl_get_dpll(struct intel_crtc_state *crtc_state,
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bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
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if (!bret) {
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DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
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return NULL;
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return false;
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}
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} else if (intel_crtc_has_dp_encoder(crtc_state)) {
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bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);
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if (!bret) {
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DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
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return NULL;
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return false;
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}
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} else {
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DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n",
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crtc_state->output_types);
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return NULL;
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return false;
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}
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pll = intel_find_shared_dpll(crtc_state,
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@ -2362,12 +2400,12 @@ cnl_get_dpll(struct intel_crtc_state *crtc_state,
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DPLL_ID_SKL_DPLL2);
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if (!pll) {
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DRM_DEBUG_KMS("No PLL selected\n");
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return NULL;
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return false;
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}
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intel_reference_shared_dpll(pll, crtc_state);
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return pll;
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return true;
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}
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static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
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@ -2394,7 +2432,8 @@ static const struct dpll_info cnl_plls[] = {
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static const struct intel_dpll_mgr cnl_pll_mgr = {
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.dpll_info = cnl_plls,
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.get_dpll = cnl_get_dpll,
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.get_dplls = cnl_get_dpll,
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.put_dplls = intel_put_dpll,
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.dump_hw_state = cnl_dump_hw_state,
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};
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@ -2792,11 +2831,13 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state)
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return true;
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}
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static struct intel_shared_dpll *
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icl_get_dpll(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
|
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static bool icl_get_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
struct intel_crtc_state *crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
struct intel_digital_port *intel_dig_port;
|
||||
struct intel_shared_dpll *pll;
|
||||
enum port port = encoder->port;
|
||||
@ -2831,24 +2872,24 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
|
||||
}
|
||||
} else {
|
||||
MISSING_CASE(port);
|
||||
return NULL;
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!ret) {
|
||||
DRM_DEBUG_KMS("Could not calculate PLL state.\n");
|
||||
return NULL;
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
pll = intel_find_shared_dpll(crtc_state, min, max);
|
||||
if (!pll) {
|
||||
DRM_DEBUG_KMS("No PLL selected\n");
|
||||
return NULL;
|
||||
return false;
|
||||
}
|
||||
|
||||
intel_reference_shared_dpll(pll, crtc_state);
|
||||
|
||||
return pll;
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
||||
@ -3223,7 +3264,8 @@ static const struct dpll_info icl_plls[] = {
|
||||
|
||||
static const struct intel_dpll_mgr icl_pll_mgr = {
|
||||
.dpll_info = icl_plls,
|
||||
.get_dpll = icl_get_dpll,
|
||||
.get_dplls = icl_get_dplls,
|
||||
.put_dplls = intel_put_dpll,
|
||||
.dump_hw_state = icl_dump_hw_state,
|
||||
};
|
||||
|
||||
@ -3235,7 +3277,8 @@ static const struct dpll_info ehl_plls[] = {
|
||||
|
||||
static const struct intel_dpll_mgr ehl_pll_mgr = {
|
||||
.dpll_info = ehl_plls,
|
||||
.get_dpll = icl_get_dpll,
|
||||
.get_dplls = icl_get_dplls,
|
||||
.put_dplls = intel_put_dpll,
|
||||
.dump_hw_state = icl_dump_hw_state,
|
||||
};
|
||||
|
||||
@ -3287,50 +3330,64 @@ void intel_shared_dpll_init(struct drm_device *dev)
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_get_shared_dpll - get a shared DPLL for CRTC and encoder combination
|
||||
* @crtc_state: atomic state for the crtc
|
||||
* intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
|
||||
* @state: atomic state
|
||||
* @crtc: CRTC to reserve DPLLs for
|
||||
* @encoder: encoder
|
||||
*
|
||||
* Find an appropriate DPLL for the given CRTC and encoder combination. A
|
||||
* reference from the @crtc_state to the returned pll is registered in the
|
||||
* atomic state. That configuration is made effective by calling
|
||||
* intel_shared_dpll_swap_state(). The reference should be released by calling
|
||||
* intel_release_shared_dpll().
|
||||
* This function reserves all required DPLLs for the given CRTC and encoder
|
||||
* combination in the current atomic commit @state and the new @crtc atomic
|
||||
* state.
|
||||
*
|
||||
* The new configuration in the atomic commit @state is made effective by
|
||||
* calling intel_shared_dpll_swap_state().
|
||||
*
|
||||
* The reserved DPLLs should be released by calling
|
||||
* intel_release_shared_dplls().
|
||||
*
|
||||
* Returns:
|
||||
* A shared DPLL to be used by @crtc_state and @encoder.
|
||||
* True if all required DPLLs were successfully reserved.
|
||||
*/
|
||||
struct intel_shared_dpll *
|
||||
intel_get_shared_dpll(struct intel_crtc_state *crtc_state,
|
||||
struct intel_encoder *encoder)
|
||||
bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
|
||||
|
||||
if (WARN_ON(!dpll_mgr))
|
||||
return NULL;
|
||||
return false;
|
||||
|
||||
return dpll_mgr->get_dpll(crtc_state, encoder);
|
||||
return dpll_mgr->get_dplls(state, crtc, encoder);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_release_shared_dpll - end use of DPLL by CRTC in atomic state
|
||||
* @dpll: dpll in use by @crtc
|
||||
* @crtc: crtc
|
||||
* intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
|
||||
* @state: atomic state
|
||||
* @crtc: crtc from which the DPLLs are to be released
|
||||
*
|
||||
* This function releases the reference from @crtc to @dpll from the
|
||||
* atomic @state. The new configuration is made effective by calling
|
||||
* intel_shared_dpll_swap_state().
|
||||
* This function releases all DPLLs reserved by intel_reserve_shared_dplls()
|
||||
* from the current atomic commit @state and the old @crtc atomic state.
|
||||
*
|
||||
* The new configuration in the atomic commit @state is made effective by
|
||||
* calling intel_shared_dpll_swap_state().
|
||||
*/
|
||||
void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
|
||||
struct intel_crtc *crtc,
|
||||
struct drm_atomic_state *state)
|
||||
void intel_release_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct intel_shared_dpll_state *shared_dpll_state;
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
|
||||
|
||||
shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
|
||||
shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
|
||||
/*
|
||||
* FIXME: this function is called for every platform having a
|
||||
* compute_clock hook, even though the platform doesn't yet support
|
||||
* the shared DPLL framework and intel_reserve_shared_dplls() is not
|
||||
* called on those.
|
||||
*/
|
||||
if (!dpll_mgr)
|
||||
return;
|
||||
|
||||
dpll_mgr->put_dplls(state, crtc);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -39,6 +39,7 @@
|
||||
struct drm_atomic_state;
|
||||
struct drm_device;
|
||||
struct drm_i915_private;
|
||||
struct intel_atomic_state;
|
||||
struct intel_crtc;
|
||||
struct intel_crtc_state;
|
||||
struct intel_encoder;
|
||||
@ -195,7 +196,7 @@ struct intel_dpll_hw_state {
|
||||
* future state which would be applied by an atomic mode set (stored in
|
||||
* a struct &intel_atomic_state).
|
||||
*
|
||||
* See also intel_get_shared_dpll() and intel_release_shared_dpll().
|
||||
* See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
|
||||
*/
|
||||
struct intel_shared_dpll_state {
|
||||
/**
|
||||
@ -331,11 +332,11 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
|
||||
bool state);
|
||||
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
|
||||
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
|
||||
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc_state *state,
|
||||
struct intel_encoder *encoder);
|
||||
void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
|
||||
struct intel_crtc *crtc,
|
||||
struct drm_atomic_state *state);
|
||||
bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder);
|
||||
void intel_release_shared_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
|
||||
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
|
||||
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user