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ARM: dts: r8a7745: Add CAN[01] SoC support
Add the definitions for can0 and can1 to the SoC .dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -1049,6 +1049,34 @@ usb2: usb-channel@2 {
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#phy-cells = <1>;
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#phy-cells = <1>;
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};
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};
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};
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};
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can0: can@e6e80000 {
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compatible = "renesas,can-r8a7745",
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"renesas,rcar-gen2-can";
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reg = <0 0xe6e80000 0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 916>,
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<&cpg CPG_CORE R8A7745_CLK_RCAN>,
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<&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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status = "disabled";
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};
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can1: can@e6e88000 {
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compatible = "renesas,can-r8a7745",
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"renesas,rcar-gen2-can";
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reg = <0 0xe6e88000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 915>,
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<&cpg CPG_CORE R8A7745_CLK_RCAN>,
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<&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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status = "disabled";
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};
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};
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};
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/* External root clock */
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/* External root clock */
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@ -1066,6 +1094,14 @@ usb_extal_clk: usb_extal {
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clock-frequency = <48000000>;
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clock-frequency = <48000000>;
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};
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};
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/* External CAN clock */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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/* External SCIF clock */
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/* External SCIF clock */
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scif_clk: scif {
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scif_clk: scif {
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compatible = "fixed-clock";
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compatible = "fixed-clock";
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