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drm/amd/display: Move MAX_TMDS_CLOCK define to header
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1360,9 +1360,6 @@ bool dc_is_stream_scaling_unchanged(
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return true;
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}
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/* Maximum TMDS single link pixel clock 165MHz */
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#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
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static void update_stream_engine_usage(
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struct resource_context *res_ctx,
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const struct resource_pool *pool,
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@ -82,13 +82,6 @@
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#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
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#define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
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/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
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#define TMDS_MIN_PIXEL_CLOCK 25000
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/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
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#define TMDS_MAX_PIXEL_CLOCK 165000
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/* For current ASICs pixel clock - 600MHz */
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#define MAX_ENCODER_CLOCK 600000
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enum {
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DP_MST_UPDATE_MAX_RETRY = 50
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};
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@ -419,11 +419,6 @@ struct bios_event_info {
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bool backlight_changed;
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};
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enum {
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HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
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TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
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};
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/*
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* DFS-bypass flag
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*/
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@ -26,6 +26,11 @@
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#ifndef __DC_SIGNAL_TYPES_H__
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#define __DC_SIGNAL_TYPES_H__
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/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
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#define TMDS_MIN_PIXEL_CLOCK 25000
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/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
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#define TMDS_MAX_PIXEL_CLOCK 165000
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enum signal_type {
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SIGNAL_TYPE_NONE = 0L, /* no signal */
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SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0),
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