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powerpc/powernv/pci: Add device to iommu group during dma_dev_setup()
Historically adding devices to their respective iommu group has been
handled by the post-init phb fixup for most devices. This was done
because:
1) The IOMMU group is tied to the PE (usually) so we can only setup the
iommu groups after we've done resource allocation since BAR location
determines the device's PE, and:
2) The sysfs directory for the pci_dev needs to be available since
iommu_add_device() wants to add an attribute for the iommu group.
However, since commit 30d87ef8b3
("powerpc/pci: Fix
pcibios_setup_device() ordering") both conditions are met when
hose->ops->dma_dev_setup() is called so there's no real need to do
this in the fixup.
Moving the call to iommu_add_device() into pnv_pci_ioda_dma_setup_dev()
is a nice cleanup since it puts all the per-device IOMMU setup into one
place. It also results in all (non-nvlink) devices getting their iommu
group via a common path rather than relying on the bus notifier hack
in pnv_tce_iommu_bus_notifier() to handle the adding VFs and
hotplugged devices to their group.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200406030745.24595-5-oohall@gmail.com
This commit is contained in:
parent
9b9408c559
commit
84d8cc0767
@ -469,6 +469,12 @@ struct iommu_table_group *pnv_try_setup_npu_table_group(struct pnv_ioda_pe *pe)
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compound_group->pgsizes = pe->table_group.pgsizes;
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}
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/*
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* The gpu would have been added to the iommu group that's created
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* for the PE. Pull it out now.
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*/
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iommu_del_device(&gpdev->dev);
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/*
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* I'm not sure this is strictly required, but it's probably a good idea
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* since the table_group for the PE is going to be attached to the
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@ -478,7 +484,9 @@ struct iommu_table_group *pnv_try_setup_npu_table_group(struct pnv_ioda_pe *pe)
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*/
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iommu_group_put(pe->table_group.group);
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/* now put the GPU into the compound group */
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pnv_comp_attach_table_group(npucomp, pe);
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iommu_add_device(compound_group, &gpdev->dev);
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return compound_group;
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}
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@ -1774,12 +1774,10 @@ static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev)
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WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
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pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
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set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
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/*
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* Note: iommu_add_device() will fail here as
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* for physical PE: the device is already added by now;
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* for virtual PE: sysfs entries are not ready yet and
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* tce_iommu_bus_notifier will add the device to a group later.
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*/
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/* PEs with a DMA weight of zero won't have a group */
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if (pe->table_group.group)
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iommu_add_device(&pe->table_group, &pdev->dev);
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}
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/*
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@ -2628,39 +2626,20 @@ static void pnv_pci_ioda_setup_iommu_api(void)
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struct pnv_ioda_pe *pe;
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/*
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* There are 4 types of PEs:
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* - PNV_IODA_PE_BUS: a downstream port with an adapter,
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* created from pnv_pci_setup_bridge();
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* - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
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* created from pnv_pci_setup_bridge();
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* - PNV_IODA_PE_VF: a SRIOV virtual function,
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* created from pnv_pcibios_sriov_enable();
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* - PNV_IODA_PE_DEV: an NPU or OCAPI device,
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* created from pnv_pci_ioda_fixup().
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* For non-nvlink devices the IOMMU group is registered when the PE is
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* configured and devices are added to the group when the per-device
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* DMA setup is run. That's done in hose->ops.dma_dev_setup() which is
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* only initialise for "normal" IODA PHBs.
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*
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* Normally a PE is represented by an IOMMU group, however for
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* devices with side channels the groups need to be more strict.
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* For NVLink devices we need to ensure the NVLinks and the GPU end up
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* in the same IOMMU group, so that's handled here.
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*/
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list_for_each_entry(hose, &hose_list, list_node) {
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phb = hose->private_data;
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if (phb->type == PNV_PHB_NPU_NVLINK ||
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phb->type == PNV_PHB_NPU_OCAPI)
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continue;
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list_for_each_entry(pe, &phb->ioda.pe_list, list) {
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struct iommu_table_group *table_group;
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table_group = pnv_try_setup_npu_table_group(pe);
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if (!table_group) {
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if (!pnv_pci_ioda_pe_dma_weight(pe))
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continue;
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table_group = &pe->table_group;
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}
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pnv_ioda_setup_bus_iommu_group(pe, table_group,
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pe->pbus);
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}
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if (phb->type == PNV_PHB_IODA2)
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list_for_each_entry(pe, &phb->ioda.pe_list, list)
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pnv_try_setup_npu_table_group(pe);
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}
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/*
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@ -955,28 +955,8 @@ static int pnv_tce_iommu_bus_notifier(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct device *dev = data;
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struct pci_dev *pdev;
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struct pci_dn *pdn;
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struct pnv_ioda_pe *pe;
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struct pci_controller *hose;
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struct pnv_phb *phb;
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switch (action) {
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case BUS_NOTIFY_ADD_DEVICE:
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pdev = to_pci_dev(dev);
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pdn = pci_get_pdn(pdev);
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hose = pci_bus_to_host(pdev->bus);
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phb = hose->private_data;
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WARN_ON_ONCE(!phb);
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if (!pdn || pdn->pe_number == IODA_INVALID_PE || !phb)
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return 0;
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pe = &phb->ioda.pe_array[pdn->pe_number];
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if (!pe->table_group.group)
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return 0;
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iommu_add_device(&pe->table_group, dev);
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return 0;
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case BUS_NOTIFY_DEL_DEVICE:
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iommu_del_device(dev);
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return 0;
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