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drm/msm/a6xx: Add support for per-instance pagetables
Add support for using per-instance pagetables if all the dependencies are available. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Akhil P Oommen <akhilpo@codeaurora.org>
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@ -81,6 +81,49 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
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OUT_RING(ring, upper_32_bits(iova));
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}
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static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
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struct msm_ringbuffer *ring, struct msm_file_private *ctx)
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{
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phys_addr_t ttbr;
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u32 asid;
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u64 memptr = rbmemptr(ring, ttbr0);
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if (ctx == a6xx_gpu->cur_ctx)
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return;
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if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
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return;
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/* Execute the table update */
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OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
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OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
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OUT_RING(ring,
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CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
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CP_SMMU_TABLE_UPDATE_1_ASID(asid));
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OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
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OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
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/*
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* Write the new TTBR0 to the memstore. This is good for debugging.
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*/
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OUT_PKT7(ring, CP_MEM_WRITE, 4);
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OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
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OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
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OUT_RING(ring, lower_32_bits(ttbr));
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OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
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/*
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* And finally, trigger a uche flush to be sure there isn't anything
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* lingering in that part of the GPU
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*/
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OUT_PKT7(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, 0x31);
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a6xx_gpu->cur_ctx = ctx;
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}
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static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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{
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unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
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@ -90,6 +133,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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struct msm_ringbuffer *ring = submit->ring;
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unsigned int i;
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a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
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get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
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rbmemptr_stats(ring, index, cpcycles_start));
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@ -704,6 +749,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
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/* Always come up on rb 0 */
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a6xx_gpu->cur_ring = gpu->rb[0];
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a6xx_gpu->cur_ctx = NULL;
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/* Enable the SQE_to start the CP engine */
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gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
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@ -1020,6 +1067,20 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
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return (unsigned long)busy_time;
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}
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static struct msm_gem_address_space *
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a6xx_create_private_address_space(struct msm_gpu *gpu)
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{
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struct msm_mmu *mmu;
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mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
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if (IS_ERR(mmu))
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return ERR_CAST(mmu);
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return msm_gem_address_space_create(mmu,
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"gpu", 0x100000000ULL, 0x1ffffffffULL);
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}
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static const struct adreno_gpu_funcs funcs = {
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.base = {
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.get_param = adreno_get_param,
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@ -1043,6 +1104,7 @@ static const struct adreno_gpu_funcs funcs = {
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.gpu_state_put = a6xx_gpu_state_put,
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#endif
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.create_address_space = adreno_iommu_create_address_space,
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.create_private_address_space = a6xx_create_private_address_space,
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},
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.get_timestamp = a6xx_get_timestamp,
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};
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@ -19,6 +19,7 @@ struct a6xx_gpu {
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uint64_t sqe_iova;
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struct msm_ringbuffer *cur_ring;
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struct msm_file_private *cur_ctx;
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struct a6xx_gmu gmu;
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};
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@ -31,6 +31,7 @@ struct msm_rbmemptrs {
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volatile uint32_t fence;
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volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT];
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volatile u64 ttbr0;
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};
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struct msm_ringbuffer {
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