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clk: qcom: lcc-msm8960: Fix PLL rate detection

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regmap_read() returns 0 on success, not the value of the register
that is read. Fix it so we properly detect the frequency plan.

Fixes: b82875ee07 "clk: qcom: Add MSM8960/APQ8064 LPASS clock
controller (LCC) driver"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
This commit is contained in:
Stephen Boyd 2015-01-29 15:38:12 -08:00 committed by Michael Turquette
parent 7dd47b8ef5
commit 84b919fdb8
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/qcom/lcc-msm8960.c
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@ -547,7 +547,7 @@ static int lcc_msm8960_probe(struct platform_device *pdev)
return PTR_ERR(regmap); return PTR_ERR(regmap);
/* Use the correct frequency plan depending on speed of PLL4 */ /* Use the correct frequency plan depending on speed of PLL4 */
val = regmap_read(regmap, 0x4, &val); regmap_read(regmap, 0x4, &val);
if (val == 0x12) { if (val == 0x12) {
slimbus_src.freq_tbl = clk_tbl_aif_osr_492; slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492; mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;