mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
drm/i915/bios: sort BDB block definitions using block ID
Make it easier to find the right blocks. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/56e1989940d83a670d087d531b7b6aa5dc4c0228.1559308269.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
231dcffc23
commit
843444ed13
@ -455,6 +455,211 @@ struct bdb_general_definitions {
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u8 devices[0];
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} __packed;
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/*
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* Block 9 - SRD Feature Block
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*/
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struct psr_table {
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/* Feature bits */
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u8 full_link:1;
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u8 require_aux_to_wakeup:1;
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u8 feature_bits_rsvd:6;
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/* Wait times */
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u8 idle_frames:4;
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u8 lines_to_wait:3;
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u8 wait_times_rsvd:1;
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/* TP wake up time in multiple of 100 */
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u16 tp1_wakeup_time;
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u16 tp2_tp3_wakeup_time;
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/* PSR2 TP2/TP3 wakeup time for 16 panels */
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u32 psr2_tp2_tp3_wakeup_time;
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} __packed;
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struct bdb_psr {
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struct psr_table psr_table[16];
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} __packed;
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/*
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* Block 12 - Driver Features Data Block
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*/
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#define BDB_DRIVER_FEATURE_NO_LVDS 0
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#define BDB_DRIVER_FEATURE_INT_LVDS 1
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#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
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#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3
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struct bdb_driver_features {
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u8 boot_dev_algorithm:1;
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u8 block_display_switch:1;
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u8 allow_display_switch:1;
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u8 hotplug_dvo:1;
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u8 dual_view_zoom:1;
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u8 int15h_hook:1;
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u8 sprite_in_clone:1;
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u8 primary_lfp_id:1;
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u16 boot_mode_x;
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u16 boot_mode_y;
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u8 boot_mode_bpp;
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u8 boot_mode_refresh;
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u16 enable_lfp_primary:1;
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u16 selective_mode_pruning:1;
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u16 dual_frequency:1;
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u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
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u16 nt_clone_support:1;
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u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
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u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
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u16 cui_aspect_scaling:1;
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u16 preserve_aspect_ratio:1;
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u16 sdvo_device_power_down:1;
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u16 crt_hotplug:1;
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u16 lvds_config:2;
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u16 tv_hotplug:1;
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u16 hdmi_config:2;
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u8 static_display:1;
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u8 reserved2:7;
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u16 legacy_crt_max_x;
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u16 legacy_crt_max_y;
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u8 legacy_crt_max_refresh;
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u8 hdmi_termination;
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u8 custom_vbt_version;
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/* Driver features data block */
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u16 rmpm_enabled:1;
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u16 s2ddt_enabled:1;
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u16 dpst_enabled:1;
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u16 bltclt_enabled:1;
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u16 adb_enabled:1;
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u16 drrs_enabled:1;
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u16 grs_enabled:1;
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u16 gpmt_enabled:1;
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u16 tbt_enabled:1;
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u16 psr_enabled:1;
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u16 ips_enabled:1;
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u16 reserved3:4;
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u16 pc_feature_valid:1;
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} __packed;
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/*
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* Block 22 - SDVO LVDS General Options
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*/
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struct bdb_sdvo_lvds_options {
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u8 panel_backlight;
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u8 h40_set_panel_type;
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u8 panel_type;
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u8 ssc_clk_freq;
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u16 als_low_trip;
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u16 als_high_trip;
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u8 sclalarcoeff_tab_row_num;
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u8 sclalarcoeff_tab_row_size;
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u8 coefficient[8];
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u8 panel_misc_bits_1;
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u8 panel_misc_bits_2;
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u8 panel_misc_bits_3;
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u8 panel_misc_bits_4;
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} __packed;
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/*
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* Block 23 - SDVO LVDS Panel DTDs
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*/
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struct lvds_dvo_timing {
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u16 clock; /**< In 10khz */
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u8 hactive_lo;
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u8 hblank_lo;
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u8 hblank_hi:4;
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u8 hactive_hi:4;
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u8 vactive_lo;
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u8 vblank_lo;
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u8 vblank_hi:4;
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u8 vactive_hi:4;
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u8 hsync_off_lo;
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u8 hsync_pulse_width_lo;
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u8 vsync_pulse_width_lo:4;
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u8 vsync_off_lo:4;
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u8 vsync_pulse_width_hi:2;
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u8 vsync_off_hi:2;
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u8 hsync_pulse_width_hi:2;
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u8 hsync_off_hi:2;
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u8 himage_lo;
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u8 vimage_lo;
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u8 vimage_hi:4;
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u8 himage_hi:4;
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u8 h_border;
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u8 v_border;
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u8 rsvd1:3;
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u8 digital:2;
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u8 vsync_positive:1;
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u8 hsync_positive:1;
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u8 non_interlaced:1;
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} __packed;
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struct bdb_sdvo_panel_dtds {
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struct lvds_dvo_timing dtds[4];
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} __packed;
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/*
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* Block 27 - eDP VBT Block
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*/
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#define EDP_18BPP 0
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#define EDP_24BPP 1
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#define EDP_30BPP 2
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#define EDP_RATE_1_62 0
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#define EDP_RATE_2_7 1
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#define EDP_LANE_1 0
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#define EDP_LANE_2 1
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#define EDP_LANE_4 3
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#define EDP_PREEMPHASIS_NONE 0
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#define EDP_PREEMPHASIS_3_5dB 1
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#define EDP_PREEMPHASIS_6dB 2
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#define EDP_PREEMPHASIS_9_5dB 3
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#define EDP_VSWING_0_4V 0
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#define EDP_VSWING_0_6V 1
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#define EDP_VSWING_0_8V 2
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#define EDP_VSWING_1_2V 3
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struct edp_fast_link_params {
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u8 rate:4;
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u8 lanes:4;
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u8 preemphasis:4;
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u8 vswing:4;
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} __packed;
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struct edp_pwm_delays {
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u16 pwm_on_to_backlight_enable;
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u16 backlight_disable_to_pwm_off;
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} __packed;
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struct edp_full_link_params {
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u8 preemphasis:4;
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u8 vswing:4;
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} __packed;
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struct bdb_edp {
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struct edp_power_seq power_seqs[16];
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u32 color_depth;
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struct edp_fast_link_params fast_link_params[16];
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u32 sdrrs_msa_timing_delay;
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/* ith bit indicates enabled/disabled for (i+1)th panel */
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u16 edp_s3d_feature; /* 162 */
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u16 edp_t3_optimization; /* 165 */
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u64 edp_vswing_preemph; /* 173 */
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u16 fast_link_training; /* 182 */
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u16 dpcd_600h_write_required; /* 185 */
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struct edp_pwm_delays pwm_delays[16]; /* 186 */
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u16 full_link_params_provided; /* 199 */
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struct edp_full_link_params full_link_params[16]; /* 199 */
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} __packed;
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/*
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* Block 40 - LFP Data Block
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*/
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@ -528,37 +733,6 @@ struct lvds_fp_timing {
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u16 terminator;
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} __packed;
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struct lvds_dvo_timing {
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u16 clock; /**< In 10khz */
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u8 hactive_lo;
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u8 hblank_lo;
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u8 hblank_hi:4;
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u8 hactive_hi:4;
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u8 vactive_lo;
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u8 vblank_lo;
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u8 vblank_hi:4;
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u8 vactive_hi:4;
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u8 hsync_off_lo;
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u8 hsync_pulse_width_lo;
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u8 vsync_pulse_width_lo:4;
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u8 vsync_off_lo:4;
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u8 vsync_pulse_width_hi:2;
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u8 vsync_off_hi:2;
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u8 hsync_pulse_width_hi:2;
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u8 hsync_off_hi:2;
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u8 himage_lo;
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u8 vimage_lo;
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u8 vimage_hi:4;
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u8 himage_hi:4;
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u8 h_border;
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u8 v_border;
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u8 rsvd1:3;
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u8 digital:2;
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u8 vsync_positive:1;
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u8 hsync_positive:1;
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u8 non_interlaced:1;
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} __packed;
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struct lvds_pnp_id {
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u16 mfg_name;
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u16 product_code;
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@ -577,14 +751,6 @@ struct bdb_lvds_lfp_data {
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struct lvds_lfp_data_entry data[16];
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} __packed;
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/*
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* Block 23 - SDVO LVDS Panel DTDs
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*/
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struct bdb_sdvo_panel_dtds {
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struct lvds_dvo_timing dtds[4];
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} __packed;
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/*
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* Block 43 - LFP Backlight Control Data Block
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*/
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@ -614,172 +780,6 @@ struct bdb_lfp_backlight_data {
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struct lfp_backlight_control_method backlight_control[16];
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} __packed;
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/*
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* Block 22 - SDVO LVDS General Options
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*/
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struct bdb_sdvo_lvds_options {
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u8 panel_backlight;
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u8 h40_set_panel_type;
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u8 panel_type;
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u8 ssc_clk_freq;
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u16 als_low_trip;
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u16 als_high_trip;
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u8 sclalarcoeff_tab_row_num;
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u8 sclalarcoeff_tab_row_size;
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u8 coefficient[8];
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u8 panel_misc_bits_1;
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u8 panel_misc_bits_2;
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u8 panel_misc_bits_3;
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u8 panel_misc_bits_4;
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} __packed;
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/*
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* Block 12 - Driver Features Data Block
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*/
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#define BDB_DRIVER_FEATURE_NO_LVDS 0
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#define BDB_DRIVER_FEATURE_INT_LVDS 1
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#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
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#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3
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struct bdb_driver_features {
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u8 boot_dev_algorithm:1;
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u8 block_display_switch:1;
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u8 allow_display_switch:1;
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u8 hotplug_dvo:1;
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u8 dual_view_zoom:1;
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u8 int15h_hook:1;
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u8 sprite_in_clone:1;
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u8 primary_lfp_id:1;
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u16 boot_mode_x;
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u16 boot_mode_y;
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u8 boot_mode_bpp;
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u8 boot_mode_refresh;
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u16 enable_lfp_primary:1;
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u16 selective_mode_pruning:1;
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u16 dual_frequency:1;
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u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
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u16 nt_clone_support:1;
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u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
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u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
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u16 cui_aspect_scaling:1;
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u16 preserve_aspect_ratio:1;
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u16 sdvo_device_power_down:1;
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u16 crt_hotplug:1;
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u16 lvds_config:2;
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u16 tv_hotplug:1;
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u16 hdmi_config:2;
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u8 static_display:1;
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u8 reserved2:7;
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u16 legacy_crt_max_x;
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u16 legacy_crt_max_y;
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u8 legacy_crt_max_refresh;
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u8 hdmi_termination;
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u8 custom_vbt_version;
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/* Driver features data block */
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u16 rmpm_enabled:1;
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u16 s2ddt_enabled:1;
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u16 dpst_enabled:1;
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u16 bltclt_enabled:1;
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u16 adb_enabled:1;
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u16 drrs_enabled:1;
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u16 grs_enabled:1;
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u16 gpmt_enabled:1;
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u16 tbt_enabled:1;
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u16 psr_enabled:1;
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u16 ips_enabled:1;
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u16 reserved3:4;
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u16 pc_feature_valid:1;
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} __packed;
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/*
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* Block 27 - eDP VBT Block
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*/
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#define EDP_18BPP 0
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#define EDP_24BPP 1
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#define EDP_30BPP 2
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#define EDP_RATE_1_62 0
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#define EDP_RATE_2_7 1
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#define EDP_LANE_1 0
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#define EDP_LANE_2 1
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#define EDP_LANE_4 3
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#define EDP_PREEMPHASIS_NONE 0
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#define EDP_PREEMPHASIS_3_5dB 1
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#define EDP_PREEMPHASIS_6dB 2
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#define EDP_PREEMPHASIS_9_5dB 3
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#define EDP_VSWING_0_4V 0
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#define EDP_VSWING_0_6V 1
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#define EDP_VSWING_0_8V 2
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#define EDP_VSWING_1_2V 3
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struct edp_fast_link_params {
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u8 rate:4;
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u8 lanes:4;
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u8 preemphasis:4;
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u8 vswing:4;
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} __packed;
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struct edp_pwm_delays {
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u16 pwm_on_to_backlight_enable;
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u16 backlight_disable_to_pwm_off;
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} __packed;
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struct edp_full_link_params {
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u8 preemphasis:4;
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u8 vswing:4;
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} __packed;
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struct bdb_edp {
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struct edp_power_seq power_seqs[16];
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u32 color_depth;
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struct edp_fast_link_params fast_link_params[16];
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u32 sdrrs_msa_timing_delay;
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/* ith bit indicates enabled/disabled for (i+1)th panel */
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u16 edp_s3d_feature; /* 162 */
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u16 edp_t3_optimization; /* 165 */
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u64 edp_vswing_preemph; /* 173 */
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u16 fast_link_training; /* 182 */
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u16 dpcd_600h_write_required; /* 185 */
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struct edp_pwm_delays pwm_delays[16]; /* 186 */
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u16 full_link_params_provided; /* 199 */
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struct edp_full_link_params full_link_params[16]; /* 199 */
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} __packed;
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/*
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* Block 9 - SRD Feature Block
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*/
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struct psr_table {
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/* Feature bits */
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u8 full_link:1;
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u8 require_aux_to_wakeup:1;
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u8 feature_bits_rsvd:6;
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/* Wait times */
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u8 idle_frames:4;
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u8 lines_to_wait:3;
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u8 wait_times_rsvd:1;
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/* TP wake up time in multiple of 100 */
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u16 tp1_wakeup_time;
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u16 tp2_tp3_wakeup_time;
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/* PSR2 TP2/TP3 wakeup time for 16 panels */
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u32 psr2_tp2_tp3_wakeup_time;
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} __packed;
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struct bdb_psr {
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struct psr_table psr_table[16];
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} __packed;
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/*
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* Block 52 - MIPI Configuration Block
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*/
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