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ath9k_hw: config diversity based on eeprom contents
* enable LNA-diversity, fast-diversity for AR9485 based on the value read from EEPROM content * if antenna diversity/combining is supported, set LNA1 for the main antenna and LNA2 for the alternate antenna based on the new diversity algorithm Cc: Gabriel Tseng <Gabriel.Tseng@Atheros.com> Cc: Senthilkumar Balasubramanian <Senthilkumar.Balasubramanian@Atheros.com> Cc: Luis Rodriguez <Luis.Rodriguez@Atheros.com> Signed-off-by: Mohammed Shafi Shajakhan <mshajakhan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -3498,6 +3498,8 @@ static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
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static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
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{
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int chain;
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u32 regval;
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u32 ant_div_ctl1;
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static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
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AR_PHY_SWITCH_CHAIN_0,
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AR_PHY_SWITCH_CHAIN_1,
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@ -3523,13 +3525,49 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
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if (AR_SREV_9485(ah)) {
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value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
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REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
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value);
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REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
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value >> 6);
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REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
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value >> 7);
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/*
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* main_lnaconf, alt_lnaconf, main_tb, alt_tb
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* are the fields present
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*/
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regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
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regval &= (~AR_ANT_DIV_CTRL_ALL);
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regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
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/* enable_lnadiv */
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regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
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regval |= ((value >> 6) & 0x1) <<
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AR_PHY_9485_ANT_DIV_LNADIV_S;
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REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
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/*enable fast_div */
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regval = REG_READ(ah, AR_PHY_CCK_DETECT);
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regval &= (~AR_FAST_DIV_ENABLE);
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regval |= ((value >> 7) & 0x1) <<
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AR_FAST_DIV_ENABLE_S;
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REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
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ant_div_ctl1 =
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ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
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/* check whether antenna diversity is enabled */
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if ((ant_div_ctl1 >> 0x6) == 0x3) {
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regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
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/*
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* clear bits 25-30 main_lnaconf, alt_lnaconf,
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* main_tb, alt_tb
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*/
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regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
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AR_PHY_9485_ANT_DIV_ALT_LNACONF |
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AR_PHY_9485_ANT_DIV_ALT_GAINTB |
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AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
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/* by default use LNA1 for the main antenna */
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regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
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AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
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regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
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AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
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REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
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}
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}
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}
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static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
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