mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 10:46:48 +07:00
Merge remote branch 'kumar/merge' into merge
This commit is contained in:
Benjamin Herrenschmidt
commit
83ebb3e344
@ -1,7 +1,7 @@
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/*
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* P1020 RDB Device Tree Source
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*
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* Copyright 2009 Freescale Semiconductor Inc.
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -553,7 +553,7 @@ pci0: pcie@ffe09000 {
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reg = <0 0xffe09000 0 0x1000>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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@ -580,8 +580,8 @@ pci1: pcie@ffe0a000 {
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#address-cells = <3>;
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reg = <0 0xffe0a000 0 0x1000>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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@ -590,8 +590,8 @@ pcie@0 {
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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@ -1,7 +1,7 @@
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/*
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* P2020 RDB Device Tree Source
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*
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* Copyright 2009 Freescale Semiconductor Inc.
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -537,7 +537,7 @@ pci0: pcie@ffe09000 {
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reg = <0 0xffe09000 0 0x1000>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <25 2>;
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@ -564,8 +564,8 @@ pci1: pcie@ffe0a000 {
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#address-cells = <3>;
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reg = <0 0xffe0a000 0 0x1000>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <26 2>;
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@ -574,8 +574,8 @@ pcie@0 {
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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@ -6,7 +6,7 @@
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* This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
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* eth1, eth2, sdhc, crypto, global-util, pci0.
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*
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* Copyright 2009 Freescale Semiconductor Inc.
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -342,7 +342,7 @@ pci0: pcie@ffe09000 {
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reg = <0 0xffe09000 0 0x1000>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <25 2>;
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@ -7,7 +7,7 @@
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*
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* Please note to add "-b 1" for core1's dts compiling.
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*
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* Copyright 2009 Freescale Semiconductor Inc.
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -162,8 +162,8 @@ pci1: pcie@ffe0a000 {
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#address-cells = <3>;
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reg = <0 0xffe0a000 0 0x1000>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <26 2>;
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@ -172,8 +172,8 @@ pcie@0 {
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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@ -1147,13 +1147,14 @@ static struct platform_driver mpc85xx_mc_err_driver = {
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static void __init mpc85xx_mc_clear_rfxe(void *data)
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{
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orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
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mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
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mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
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}
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#endif
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static int __init mpc85xx_mc_init(void)
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{
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int res = 0;
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u32 pvr = 0;
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printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
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"(C) 2006 Montavista Software\n");
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@ -1183,12 +1184,17 @@ static int __init mpc85xx_mc_init(void)
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#endif
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#ifdef CONFIG_FSL_SOC_BOOKE
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/*
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* need to clear HID1[RFXE] to disable machine check int
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* so we can catch it
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*/
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if (edac_op_state == EDAC_OPSTATE_INT)
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on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
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pvr = mfspr(SPRN_PVR);
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if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
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(PVR_VER(pvr) == PVR_VER_E500V2)) {
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/*
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* need to clear HID1[RFXE] to disable machine check int
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* so we can catch it
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*/
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if (edac_op_state == EDAC_OPSTATE_INT)
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on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
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}
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#endif
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return 0;
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@ -1206,7 +1212,12 @@ static void __exit mpc85xx_mc_restore_hid1(void *data)
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static void __exit mpc85xx_mc_exit(void)
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{
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#ifdef CONFIG_FSL_SOC_BOOKE
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on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
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u32 pvr = mfspr(SPRN_PVR);
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if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
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(PVR_VER(pvr) == PVR_VER_E500V2)) {
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on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
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}
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#endif
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#ifdef CONFIG_PCI
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platform_driver_unregister(&mpc85xx_pci_err_driver);
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