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edac: driver for i5400 MCH (update)
Signed-off-by: Ben Woodard <woodard@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> Cc: Doug Thompson <norsk5@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Mauro Carvalho Chehab
Linus Torvalds
parent
920c8df6ac
commit
8375d4909a
@ -1,5 +1,5 @@
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/*
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* Intel 5400 class Memory Controllers kernel module
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* Intel 5400 class Memory Controllers kernel module (Seaburg)
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*
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* This file may be distributed under the terms of the
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* GNU General Public License.
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@ -55,13 +55,11 @@
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* Function 1: Memory Branch Map, Control, Errors Register
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* Function 2: FSB Error Registers
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*
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* All 3 functions of Device 16 (0,1,2) share the SAME DID
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* All 3 functions of Device 16 (0,1,2) share the SAME DID and
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* uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2),
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* PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1
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* for device 21 (0,1).
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*/
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#ifndef PCI_DEVICE_ID_INTEL_5400_ERR
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#define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030 /* Device 16 (0,1,2) */
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#define PCI_DEVICE_ID_INTEL_5400_FBD0 0x4035 /* Device 21 (0,1) */
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#define PCI_DEVICE_ID_INTEL_5400_FBD1 0x4036 /* Device 21 (0,1) */
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#endif
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/* OFFSETS for Function 0 */
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#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
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@ -174,17 +172,17 @@ enum error_mask {
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/*
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* Names to translate bit error into something useful
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*/
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char *error_name[] = {
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static const char *error_name[] = {
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[0] = "Memory Write error on non-redundant retry",
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[1] = "Memory or FB-DIMM configuration CRC read error",
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/* Reserved */
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[3] = "Uncorrectable Data ECC on Replay",
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[4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
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/* Unsupported on i5400 */
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/* M6 Unsupported on i5400 */
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[6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
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[7] = "Aliased Uncorrectable Patrol Data ECC",
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[8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
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/* Unsupported */
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/* M10 Unsupported on i5400 */
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[10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
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[11] = "Non-Aliased Uncorrectable Patrol Data ECC",
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[12] = "Memory Write error on first attempt",
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@ -192,7 +190,7 @@ char *error_name[] = {
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[14] = "Memory or FB-DIMM configuration CRC read error",
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[15] = "Channel Failed-Over Occurred",
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[16] = "Correctable Non-Mirrored Demand Data ECC",
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/* Unsupported */
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/* M18 Unsupported on i5400 */
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[18] = "Correctable Resilver- or Spare-Copy Data ECC",
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[19] = "Correctable Patrol Data ECC",
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[20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
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@ -259,24 +257,32 @@ char *error_name[] = {
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#define FERR_FAT_MASK ERROR_FAT_MASK
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/* masks for non-fatal error register */
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#define TO_NF_MASK(a) (((a) & EMASK_M29) | ((a) >> 3))
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#define FROM_NF_FERR(a) (((a) & EMASK_M29) | (((a) << 3) & ((1 << 30)-1)))
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static inline int to_nf_mask(unsigned int mask)
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{
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return (mask & EMASK_M29) | (mask >> 3);
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};
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#define FERR_NF_MASK TO_NF_MASK(ERROR_NF_MASK)
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#define FERR_NF_CORRECTABLE TO_NF_MASK(ERROR_NF_CORRECTABLE)
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#define FERR_NF_DIMM_SPARE TO_NF_MASK(ERROR_NF_DIMM_SPARE)
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#define FERR_NF_SPD_PROTOCOL TO_NF_MASK(ERROR_NF_SPD_PROTOCOL)
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#define FERR_NF_NORTH_CRC TO_NF_MASK(ERROR_NF_NORTH_CRC)
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#define FERR_NF_RECOVERABLE TO_NF_MASK(ERROR_NF_RECOVERABLE)
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#define FERR_NF_UNCORRECTABLE TO_NF_MASK(ERROR_NF_UNCORRECTABLE)
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static inline int from_nf_ferr(unsigned int mask)
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{
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return (mask & EMASK_M29) | /* Bit 28 */
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(mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */
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};
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#define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)
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#define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)
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#define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)
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#define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)
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#define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)
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#define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)
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#define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)
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/* Defines to extract the vaious fields from the
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* MTRx - Memory Technology Registers
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*/
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#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10))
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#define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9))
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#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1<< 8)) ? 8 : 4)
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#define MTR_DRAM_BANKS(mtr) (((mtr) & (1<< 6)) ? 8 : 4)
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#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4)
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#define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
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#define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
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#define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1)
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#define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
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@ -293,7 +299,7 @@ static inline int extract_fbdchan_indx(u32 x)
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#ifdef CONFIG_EDAC_DEBUG
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/* MTR NUMROW */
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static char *numrow_toString[] = {
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static const char *numrow_toString[] = {
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"8,192 - 13 rows",
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"16,384 - 14 rows",
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"32,768 - 15 rows",
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@ -301,7 +307,7 @@ static char *numrow_toString[] = {
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};
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/* MTR NUMCOL */
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static char *numcol_toString[] = {
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static const char *numcol_toString[] = {
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"1,024 - 10 columns",
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"2,048 - 11 columns",
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"4,096 - 12 columns",
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@ -341,11 +347,11 @@ struct i5400_pvt {
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u16 mir0, mir1;
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u16 b0_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
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u16 b0_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
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u16 b0_ambpresent0; /* Branch 0, Channel 0 */
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u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
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u16 b1_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
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u16 b1_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
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u16 b1_ambpresent0; /* Branch 1, Channel 8 */
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u16 b1_ambpresent1; /* Branch 1, Channel 1 */
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@ -370,7 +376,7 @@ struct i5400_error_info {
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u16 recmema; /* Recoverable Mem Error log A */
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u32 recmemb; /* Recoverable Mem Error log B */
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/* These registers are input ONLY if there was a Non-Recoverable Error */
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/* These registers are input ONLY if there was a Non-Rec Error */
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u16 nrecmema; /* Non-Recoverable Mem log A */
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u16 nrecmemb; /* Non-Recoverable Mem log B */
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@ -560,10 +566,10 @@ static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
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/* Form out message */
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snprintf(msg, sizeof(msg),
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"%s (Branch=%d DRAM-Bank=%d Buffer ID = %d RDWR=%s RAS=%d CAS=%d "
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"%s Err=0x%lx (%s))",
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type, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas, type,
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allErrors, error_name[errnum]);
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"%s (Branch=%d DRAM-Bank=%d Buffer ID = %d RDWR=%s "
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"RAS=%d CAS=%d %s Err=0x%lx (%s))",
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type, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas,
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type, allErrors, error_name[errnum]);
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/* Call the helper to output message */
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edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
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@ -590,7 +596,7 @@ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
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int errnum;
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/* mask off the Error bits that are possible */
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allErrors = FROM_NF_FERR(info->ferr_nf_fbd & FERR_NF_MASK);
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allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK);
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if (!allErrors)
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return; /* if no error, return now */
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@ -631,10 +637,10 @@ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
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/* Form out message */
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snprintf(msg, sizeof(msg),
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"Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
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"CAS=%d, CE Err=0x%lx (%s))", branch >> 1, bank,
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rdwr_str(rdwr), ras, cas, allErrors,
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error_name[errnum]);
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"Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s "
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"RAS=%d CAS=%d, CE Err=0x%lx (%s))",
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branch >> 1, bank, rdwr_str(rdwr), ras, cas,
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allErrors, error_name[errnum]);
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/* Call the helper to output message */
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edac_mc_handle_fbd_ce(mci, rank, channel, msg);
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@ -704,17 +710,10 @@ static void i5400_put_devices(struct mem_ctl_info *mci)
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pvt = mci->pvt_info;
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/* Decrement usage count for devices */
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if (pvt->branch_1)
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pci_dev_put(pvt->branch_1);
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if (pvt->branch_0)
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pci_dev_put(pvt->branch_0);
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if (pvt->fsb_error_regs)
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pci_dev_put(pvt->fsb_error_regs);
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if (pvt->branchmap_werrors)
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pci_dev_put(pvt->branchmap_werrors);
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pci_dev_put(pvt->branch_1);
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pci_dev_put(pvt->branch_0);
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pci_dev_put(pvt->fsb_error_regs);
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pci_dev_put(pvt->branchmap_werrors);
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}
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/*
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@ -810,9 +809,9 @@ static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
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/*
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* determine_amb_present
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*
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* the information is contained in NUM_MTRS_PER_BRANCH different registers
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* determining which of the NUM_MTRS_PER_BRANCH requires knowing
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* which channel is in question
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* the information is contained in NUM_MTRS_PER_BRANCH different
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* registers determining which of the NUM_MTRS_PER_BRANCH requires
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* knowing which channel is in question
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*
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* 2 branches, each with 2 channels
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* b0_ambpresent0 for channel '0'
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@ -842,7 +841,7 @@ static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
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/*
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* determine_mtr(pvt, csrow, channel)
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*
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* return the proper MTR register as determine by the csrow and channel desired
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* return the proper MTR register as determine by the csrow and desired channel
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*/
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static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel)
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{
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@ -857,7 +856,8 @@ static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel)
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n = csrow >> 3;
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if (n >= NUM_MTRS_PER_BRANCH) {
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debugf0("ERROR: trying to access an invalid csrow: %d\n", csrow);
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debugf0("ERROR: trying to access an invalid csrow: %d\n",
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csrow);
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return 0;
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}
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@ -885,7 +885,7 @@ static void decode_mtr(int slot_row, u16 mtr)
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debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
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debugf2("\t\tELECTRICAL THROTTLING is %s\n",
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MTR_DIMMS_ETHROTTLE(mtr) ? "enabled": "disabled");
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MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
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debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
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debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
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@ -1251,6 +1251,9 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
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int num_dimms_per_channel;
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int num_csrows;
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if (dev_idx >= ARRAY_SIZE(i5400_devs))
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return -EINVAL;
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debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
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__func__,
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pdev->bus->number,
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@ -1425,7 +1428,7 @@ MODULE_DEVICE_TABLE(pci, i5400_pci_tbl);
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*
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*/
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static struct pci_driver i5400_driver = {
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.name = KBUILD_BASENAME,
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.name = "i5400_edac",
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.probe = i5400_init_one,
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.remove = __devexit_p(i5400_remove_one),
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.id_table = i5400_pci_tbl,
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@ -1463,9 +1466,11 @@ module_init(i5400_init);
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module_exit(i5400_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ben Woodard <woodard@redhat.com> Red Hat Inc. (http://www.redhat.com)");
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MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com> Red Hat Inc. (http://www.redhat.com)");
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MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - " I5400_REVISION);
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MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>");
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MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
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MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
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MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - "
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I5400_REVISION);
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module_param(edac_op_state, int, 0444);
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MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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