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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma
Pull slave-dmaengine fixes from Vinod Koul: "Here is the slave dmanegine fixes. We have the fix for deadlock issue on imx-dma by Michael and Josh's edma config fix along with author change" * 'fixes' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: imx-dma: fix callback path in tasklet dmaengine: imx-dma: fix lockdep issue between irqhandler and tasklet dmaengine: imx-dma: fix slow path issue in prep_dma_cyclic dma/Kconfig: Make TI_EDMA select TI_PRIV_EDMA edma: Update author email address
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commit
831ae3c1df
@ -198,6 +198,7 @@ config TI_EDMA
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depends on ARCH_DAVINCI || ARCH_OMAP
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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select TI_PRIV_EDMA
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default n
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help
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Enable support for the TI EDMA controller. This DMA
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@ -749,6 +749,6 @@ static void __exit edma_exit(void)
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}
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module_exit(edma_exit);
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MODULE_AUTHOR("Matt Porter <mporter@ti.com>");
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MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
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MODULE_DESCRIPTION("TI EDMA DMA engine driver");
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MODULE_LICENSE("GPL v2");
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@ -437,17 +437,18 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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int chno = imxdmac->channel;
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struct imxdma_desc *desc;
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unsigned long flags;
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spin_lock(&imxdma->lock);
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spin_lock_irqsave(&imxdma->lock, flags);
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if (list_empty(&imxdmac->ld_active)) {
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spin_unlock(&imxdma->lock);
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spin_unlock_irqrestore(&imxdma->lock, flags);
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goto out;
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}
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desc = list_first_entry(&imxdmac->ld_active,
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struct imxdma_desc,
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node);
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spin_unlock(&imxdma->lock);
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spin_unlock_irqrestore(&imxdma->lock, flags);
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if (desc->sg) {
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u32 tmp;
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@ -519,7 +520,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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unsigned long flags;
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int slot = -1;
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int i;
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@ -527,7 +527,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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switch (d->type) {
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case IMXDMA_DESC_INTERLEAVED:
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/* Try to get a free 2D slot */
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spin_lock_irqsave(&imxdma->lock, flags);
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for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
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if ((imxdma->slots_2d[i].count > 0) &&
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((imxdma->slots_2d[i].xsr != d->x) ||
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@ -537,10 +536,8 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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slot = i;
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break;
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}
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if (slot < 0) {
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spin_unlock_irqrestore(&imxdma->lock, flags);
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if (slot < 0)
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return -EBUSY;
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}
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imxdma->slots_2d[slot].xsr = d->x;
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imxdma->slots_2d[slot].ysr = d->y;
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@ -549,7 +546,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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imxdmac->slot_2d = slot;
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imxdmac->enabled_2d = true;
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spin_unlock_irqrestore(&imxdma->lock, flags);
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if (slot == IMX_DMA_2D_SLOT_A) {
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d->config_mem &= ~CCR_MSEL_B;
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@ -625,18 +621,17 @@ static void imxdma_tasklet(unsigned long data)
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struct imxdma_channel *imxdmac = (void *)data;
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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struct imxdma_desc *desc;
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unsigned long flags;
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spin_lock(&imxdma->lock);
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spin_lock_irqsave(&imxdma->lock, flags);
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if (list_empty(&imxdmac->ld_active)) {
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/* Someone might have called terminate all */
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goto out;
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spin_unlock_irqrestore(&imxdma->lock, flags);
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return;
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}
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desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
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if (desc->desc.callback)
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desc->desc.callback(desc->desc.callback_param);
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/* If we are dealing with a cyclic descriptor, keep it on ld_active
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* and dont mark the descriptor as complete.
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* Only in non-cyclic cases it would be marked as complete
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@ -663,7 +658,11 @@ static void imxdma_tasklet(unsigned long data)
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__func__, imxdmac->channel);
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}
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out:
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spin_unlock(&imxdma->lock);
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spin_unlock_irqrestore(&imxdma->lock, flags);
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if (desc->desc.callback)
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desc->desc.callback(desc->desc.callback_param);
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}
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static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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@ -883,7 +882,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
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kfree(imxdmac->sg_list);
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imxdmac->sg_list = kcalloc(periods + 1,
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sizeof(struct scatterlist), GFP_KERNEL);
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sizeof(struct scatterlist), GFP_ATOMIC);
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if (!imxdmac->sg_list)
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return NULL;
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