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drm/amd/powerplay: enable backdoor smu fw loading (v2)
enable backdoor smu fw loading on navi10 v2: squash in define fix (Alex) Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -30,6 +30,7 @@
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#define MP0_SRAM 0x03900000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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#define MP1_SRAM 0x03c00004
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#define MP1_SMC_SIZE 0x40000
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/* address block */
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/* address block */
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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@ -207,6 +207,39 @@ static int smu_v11_0_init_microcode(struct smu_context *smu)
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static int smu_v11_0_load_microcode(struct smu_context *smu)
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static int smu_v11_0_load_microcode(struct smu_context *smu)
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{
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{
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struct amdgpu_device *adev = smu->adev;
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const uint32_t *src;
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const struct smc_firmware_header_v1_0 *hdr;
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uint32_t addr_start = MP1_SRAM;
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uint32_t i;
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uint32_t mp1_fw_flags;
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hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
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src = (const uint32_t *)(adev->pm.fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
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WREG32_PCIE(addr_start, src[i]);
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addr_start += 4;
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}
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WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
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1 & MP1_SMN_PUB_CTRL__RESET_MASK);
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WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
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1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
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for (i = 0; i < adev->usec_timeout; i++) {
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mp1_fw_flags = RREG32_PCIE(MP1_Public |
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(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
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if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
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break;
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udelay(1);
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}
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if (i == adev->usec_timeout)
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return -ETIME;
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return 0;
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return 0;
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}
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}
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