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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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net: mvpp2: unify register definitions coding style
Cosmetic patch to use the same formatting rules on all register definitions. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -193,18 +193,18 @@
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#define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0
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#define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port))
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#define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
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#define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
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#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
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#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
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#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
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#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
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#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
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#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
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#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
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#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
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#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
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#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
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#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
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#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
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#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
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#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
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#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
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#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
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#define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
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#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
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@ -272,7 +272,7 @@
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#define MVPP2_BM_VIRT_RLS_REG 0x64c0
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#define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
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#define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
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#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
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#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
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#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
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/* TX Scheduler registers */
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@ -314,57 +314,57 @@
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/* Per-port registers */
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#define MVPP2_GMAC_CTRL_0_REG 0x0
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#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
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#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
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#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
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#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
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#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
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#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
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#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
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#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
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#define MVPP2_GMAC_CTRL_1_REG 0x4
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#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
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#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
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#define MVPP2_GMAC_PCS_LB_EN_BIT 6
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#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
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#define MVPP2_GMAC_SA_LOW_OFFS 7
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#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
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#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
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#define MVPP2_GMAC_PCS_LB_EN_BIT 6
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#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
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#define MVPP2_GMAC_SA_LOW_OFFS 7
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#define MVPP2_GMAC_CTRL_2_REG 0x8
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#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
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#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
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#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
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#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
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#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
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#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
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#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
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#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
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#define MVPP2_GMAC_AUTONEG_CONFIG 0xc
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#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
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#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
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#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
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#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
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#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
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#define MVPP2_GMAC_FC_ADV_EN BIT(9)
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#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
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#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
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#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
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#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
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#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
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#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
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#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
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#define MVPP2_GMAC_FC_ADV_EN BIT(9)
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#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
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#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
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#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
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MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
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#define MVPP22_GMAC_CTRL_4_REG 0x90
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#define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
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#define MVPP22_CTRL4_DP_CLK_SEL BIT(5)
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#define MVPP22_CTRL4_SYNC_BYPASS BIT(6)
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#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
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#define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
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#define MVPP22_CTRL4_DP_CLK_SEL BIT(5)
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#define MVPP22_CTRL4_SYNC_BYPASS BIT(6)
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#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
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/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
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* relative to port->base.
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*/
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#define MVPP22_XLG_CTRL0_REG 0x100
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#define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
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#define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1)
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#define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14)
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#define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
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#define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1)
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#define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14)
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#define MVPP22_XLG_CTRL3_REG 0x11c
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#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
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#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
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#define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)
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#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
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#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
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#define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)
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/* SMI registers. PPv2.2 only, relative to priv->iface_base. */
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#define MVPP22_SMI_MISC_CFG_REG 0x1204
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#define MVPP22_SMI_POLLING_EN BIT(10)
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#define MVPP22_SMI_POLLING_EN BIT(10)
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#define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00)
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