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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions
The latest version of the Armada XP datasheet no longer documents the
VDD cpu_pd functions, which might indicate they are not working and/or
not supported. This commit ensures the pinctrl driver matches the
datasheet.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f76 ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Thomas Petazzoni
Linus Walleij
parent
bc99357f36
commit
80b3d04fea
@ -44,13 +44,13 @@ mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
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mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
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mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst)
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mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk)
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mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
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mpp26 26 gpio, lcd(clk), tdm(fsync)
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mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
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mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
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mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
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mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
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mpp30 30 gpio, tdm(int1), sd0(clk)
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mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
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mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
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mpp31 31 gpio, tdm(int2), sd0(cmd)
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mpp32 32 gpio, tdm(int3), sd0(d0)
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mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
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mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
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mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
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@ -58,14 +58,11 @@ mpp36 36 gpio, spi(mosi)
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mpp37 37 gpio, spi(miso)
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mpp38 38 gpio, spi(sck)
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mpp39 39 gpio, spi(cs0)
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mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
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pcie(clkreq0)
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mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0)
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mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
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pcie(clkreq1)
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mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
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vdd(cpu0-pd)
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mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
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vdd(cpu2-3-pd){1}
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mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer)
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mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout)
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mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
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mem(bat)
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mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
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@ -84,9 +81,9 @@ mpp51 51 gpio, dev(ad16)
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mpp52 52 gpio, dev(ad17)
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mpp53 53 gpio, dev(ad18)
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mpp54 54 gpio, dev(ad19)
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mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
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mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
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mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
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mpp55 55 gpio, dev(ad20)
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mpp56 56 gpio, dev(ad21)
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mpp57 57 gpio, dev(ad22)
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mpp58 58 gpio, dev(ad23)
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mpp59 59 gpio, dev(ad24)
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mpp60 60 gpio, dev(ad25)
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@ -96,6 +93,3 @@ mpp63 63 gpio, dev(ad28)
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mpp64 64 gpio, dev(ad29)
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mpp65 65 gpio, dev(ad30)
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mpp66 66 gpio, dev(ad31)
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Notes:
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* {1} vdd(cpu2-3-pd) only available on mv78460.
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@ -14,10 +14,7 @@
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* available: mv78230, mv78260 and mv78460. From a pin muxing
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* perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
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* both have 67 MPP pins (more GPIOs and address lines for the memory
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* bus mainly). The only difference between the mv78260 and the
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* mv78460 in terms of pin muxing is the addition of two functions on
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* pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
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* cores, mv78460 has four cores).
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* bus mainly).
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*/
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#include <linux/err.h>
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@ -182,8 +179,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
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MPP_MODE(26,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
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MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS)),
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MPP_MODE(27,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS),
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@ -198,8 +194,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
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MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)),
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MPP_MODE(30,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS),
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@ -207,13 +202,11 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
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MPP_MODE(31,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
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MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS)),
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MPP_MODE(32,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)),
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MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS)),
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MPP_MODE(33,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS),
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@ -245,7 +238,6 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)),
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MPP_MODE(41,
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@ -260,15 +252,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
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MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)),
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MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS)),
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MPP_MODE(43,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)),
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MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)),
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MPP_MODE(44,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
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MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS),
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@ -319,16 +309,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
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MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)),
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MPP_MODE(55,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
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MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS),
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MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)),
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MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS)),
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MPP_MODE(56,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
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MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS),
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MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)),
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MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS)),
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MPP_MODE(57,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
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MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS),
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MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)),
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MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS)),
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MPP_MODE(58,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
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MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)),
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