mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 09:36:46 +07:00
drm/i915: don't program FDI RX/TX in mode_set
We do this later (and more properly) when we enable FDI, so we don't need to do it here. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
parent
17f6766c62
commit
8088699f02
@ -4140,27 +4140,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
||||
|
||||
if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
|
||||
ironlake_set_pll_edp(crtc, adjusted_mode->clock);
|
||||
} else {
|
||||
/* enable FDI RX PLL too */
|
||||
reg = FDI_RX_CTL(pipe);
|
||||
temp = I915_READ(reg);
|
||||
I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
|
||||
|
||||
POSTING_READ(reg);
|
||||
udelay(200);
|
||||
|
||||
/* enable FDI TX PLL too */
|
||||
reg = FDI_TX_CTL(pipe);
|
||||
temp = I915_READ(reg);
|
||||
I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
|
||||
|
||||
/* enable FDI RX PCDCLK */
|
||||
reg = FDI_RX_CTL(pipe);
|
||||
temp = I915_READ(reg);
|
||||
I915_WRITE(reg, temp | FDI_PCDCLK);
|
||||
|
||||
POSTING_READ(reg);
|
||||
udelay(200);
|
||||
}
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user