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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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KVM: x86 emulator: Use ctxt->_eip directly in do_insn_fetch_byte()
Instead of passing ctxt->_eip from insn_fetch() call sites, get it from ctxt in do_insn_fetch_byte(). This is done by replacing the argument _eip of insn_fetch() with _ctxt, which should be better than letting the macro use ctxt silently in its body. Though this changes the place where ctxt->_eip is incremented from insn_fetch() to do_insn_fetch_byte(), this does not have any real effect. Signed-off-by: Takuya Yoshikawa <yoshikawa.takuya@oss.ntt.co.jp> Signed-off-by: Avi Kivity <avi@redhat.com>
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743eeb0b01
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@ -651,18 +651,26 @@ static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
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return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
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}
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static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt,
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unsigned long eip, u8 *dest)
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/*
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* Fetch the next byte of the instruction being emulated which is pointed to
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* by ctxt->_eip, then increment ctxt->_eip.
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*
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* Also prefetch the remaining bytes of the instruction without crossing page
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* boundary if they are not in fetch_cache yet.
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*/
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static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
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{
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struct fetch_cache *fc = &ctxt->fetch;
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int rc;
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int size, cur_size;
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if (eip == fc->end) {
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if (ctxt->_eip == fc->end) {
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unsigned long linear;
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struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
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struct segmented_address addr = { .seg = VCPU_SREG_CS,
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.ea = ctxt->_eip };
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cur_size = fc->end - fc->start;
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size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
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size = min(15UL - cur_size,
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PAGE_SIZE - offset_in_page(ctxt->_eip));
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rc = __linearize(ctxt, addr, size, false, true, &linear);
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if (rc != X86EMUL_CONTINUE)
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return rc;
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@ -672,20 +680,21 @@ static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt,
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return rc;
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fc->end += size;
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}
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*dest = fc->data[eip - fc->start];
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*dest = fc->data[ctxt->_eip - fc->start];
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ctxt->_eip++;
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return X86EMUL_CONTINUE;
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}
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static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
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unsigned long eip, void *dest, unsigned size)
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void *dest, unsigned size)
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{
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int rc;
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/* x86 instructions are limited to 15 bytes. */
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if (eip + size - ctxt->eip > 15)
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if (ctxt->_eip + size - ctxt->eip > 15)
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return X86EMUL_UNHANDLEABLE;
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while (size--) {
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rc = do_insn_fetch_byte(ctxt, eip++, dest++);
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rc = do_insn_fetch_byte(ctxt, dest++);
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if (rc != X86EMUL_CONTINUE)
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return rc;
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}
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@ -693,20 +702,18 @@ static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
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}
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/* Fetch next part of the instruction being emulated. */
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#define insn_fetch(_type, _size, _eip) \
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#define insn_fetch(_type, _size, _ctxt) \
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({ unsigned long _x; \
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rc = do_insn_fetch(ctxt, (_eip), &_x, (_size)); \
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rc = do_insn_fetch(_ctxt, &_x, (_size)); \
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if (rc != X86EMUL_CONTINUE) \
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goto done; \
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(_eip) += (_size); \
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(_type)_x; \
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})
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#define insn_fetch_arr(_arr, _size, _eip) \
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({ rc = do_insn_fetch(ctxt, (_eip), _arr, (_size)); \
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#define insn_fetch_arr(_arr, _size, _ctxt) \
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({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
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if (rc != X86EMUL_CONTINUE) \
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goto done; \
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(_eip) += (_size); \
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})
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/*
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@ -894,7 +901,7 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt,
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ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
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}
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ctxt->modrm = insn_fetch(u8, 1, ctxt->_eip);
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ctxt->modrm = insn_fetch(u8, 1, ctxt);
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ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
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ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
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ctxt->modrm_rm |= (ctxt->modrm & 0x07);
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@ -928,13 +935,13 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt,
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switch (ctxt->modrm_mod) {
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case 0:
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if (ctxt->modrm_rm == 6)
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modrm_ea += insn_fetch(u16, 2, ctxt->_eip);
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modrm_ea += insn_fetch(u16, 2, ctxt);
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break;
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case 1:
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modrm_ea += insn_fetch(s8, 1, ctxt->_eip);
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modrm_ea += insn_fetch(s8, 1, ctxt);
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break;
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case 2:
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modrm_ea += insn_fetch(u16, 2, ctxt->_eip);
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modrm_ea += insn_fetch(u16, 2, ctxt);
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break;
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}
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switch (ctxt->modrm_rm) {
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@ -971,13 +978,13 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt,
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} else {
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/* 32/64-bit ModR/M decode. */
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if ((ctxt->modrm_rm & 7) == 4) {
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sib = insn_fetch(u8, 1, ctxt->_eip);
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sib = insn_fetch(u8, 1, ctxt);
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index_reg |= (sib >> 3) & 7;
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base_reg |= sib & 7;
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scale = sib >> 6;
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if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
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modrm_ea += insn_fetch(s32, 4, ctxt->_eip);
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modrm_ea += insn_fetch(s32, 4, ctxt);
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else
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modrm_ea += ctxt->regs[base_reg];
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if (index_reg != 4)
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@ -990,13 +997,13 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt,
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switch (ctxt->modrm_mod) {
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case 0:
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if (ctxt->modrm_rm == 5)
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modrm_ea += insn_fetch(s32, 4, ctxt->_eip);
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modrm_ea += insn_fetch(s32, 4, ctxt);
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break;
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case 1:
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modrm_ea += insn_fetch(s8, 1, ctxt->_eip);
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modrm_ea += insn_fetch(s8, 1, ctxt);
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break;
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case 2:
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modrm_ea += insn_fetch(s32, 4, ctxt->_eip);
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modrm_ea += insn_fetch(s32, 4, ctxt);
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break;
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}
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}
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@ -1013,13 +1020,13 @@ static int decode_abs(struct x86_emulate_ctxt *ctxt,
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op->type = OP_MEM;
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switch (ctxt->ad_bytes) {
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case 2:
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op->addr.mem.ea = insn_fetch(u16, 2, ctxt->_eip);
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op->addr.mem.ea = insn_fetch(u16, 2, ctxt);
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break;
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case 4:
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op->addr.mem.ea = insn_fetch(u32, 4, ctxt->_eip);
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op->addr.mem.ea = insn_fetch(u32, 4, ctxt);
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break;
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case 8:
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op->addr.mem.ea = insn_fetch(u64, 8, ctxt->_eip);
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op->addr.mem.ea = insn_fetch(u64, 8, ctxt);
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break;
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}
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done:
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@ -3309,13 +3316,13 @@ static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
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/* NB. Immediates are sign-extended as necessary. */
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switch (op->bytes) {
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case 1:
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op->val = insn_fetch(s8, 1, ctxt->_eip);
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op->val = insn_fetch(s8, 1, ctxt);
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break;
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case 2:
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op->val = insn_fetch(s16, 2, ctxt->_eip);
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op->val = insn_fetch(s16, 2, ctxt);
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break;
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case 4:
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op->val = insn_fetch(s32, 4, ctxt->_eip);
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op->val = insn_fetch(s32, 4, ctxt);
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break;
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}
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if (!sign_extension) {
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@ -3374,7 +3381,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
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/* Legacy prefixes. */
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for (;;) {
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switch (ctxt->b = insn_fetch(u8, 1, ctxt->_eip)) {
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switch (ctxt->b = insn_fetch(u8, 1, ctxt)) {
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case 0x66: /* operand-size override */
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op_prefix = true;
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/* switch between 2/4 bytes */
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@ -3430,7 +3437,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
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/* Two-byte opcode? */
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if (ctxt->b == 0x0f) {
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ctxt->twobyte = 1;
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ctxt->b = insn_fetch(u8, 1, ctxt->_eip);
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ctxt->b = insn_fetch(u8, 1, ctxt);
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opcode = twobyte_table[ctxt->b];
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}
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ctxt->d = opcode.flags;
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@ -3438,13 +3445,13 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
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while (ctxt->d & GroupMask) {
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switch (ctxt->d & GroupMask) {
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case Group:
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ctxt->modrm = insn_fetch(u8, 1, ctxt->_eip);
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ctxt->modrm = insn_fetch(u8, 1, ctxt);
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--ctxt->_eip;
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goffset = (ctxt->modrm >> 3) & 7;
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opcode = opcode.u.group[goffset];
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break;
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case GroupDual:
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ctxt->modrm = insn_fetch(u8, 1, ctxt->_eip);
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ctxt->modrm = insn_fetch(u8, 1, ctxt);
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--ctxt->_eip;
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goffset = (ctxt->modrm >> 3) & 7;
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if ((ctxt->modrm >> 6) == 3)
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@ -3577,7 +3584,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
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ctxt->src.type = OP_IMM;
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ctxt->src.addr.mem.ea = ctxt->_eip;
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ctxt->src.bytes = ctxt->op_bytes + 2;
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insn_fetch_arr(ctxt->src.valptr, ctxt->src.bytes, ctxt->_eip);
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insn_fetch_arr(ctxt->src.valptr, ctxt->src.bytes, ctxt);
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break;
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case SrcMemFAddr:
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memop.bytes = ctxt->op_bytes + 2;
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@ -3630,7 +3637,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
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ctxt->dst.type = OP_IMM;
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ctxt->dst.addr.mem.ea = ctxt->_eip;
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ctxt->dst.bytes = 1;
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ctxt->dst.val = insn_fetch(u8, 1, ctxt->_eip);
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ctxt->dst.val = insn_fetch(u8, 1, ctxt);
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break;
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case DstMem:
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case DstMem64:
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