mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 10:56:45 +07:00
drm/nva3: implement support for copy engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
a82dd49f14
commit
7ff5441e55
@ -20,6 +20,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nv40_graph.o nv50_graph.o nvc0_graph.o \
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nv40_grctx.o nv50_grctx.o nvc0_grctx.o \
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nv84_crypt.o \
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nva3_copy.o \
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nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
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nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
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nv50_cursor.o nv50_display.o \
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@ -151,6 +151,8 @@ enum nouveau_flags {
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#define NVOBJ_ENGINE_SW 0
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#define NVOBJ_ENGINE_GR 1
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#define NVOBJ_ENGINE_CRYPT 2
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#define NVOBJ_ENGINE_COPY0 3
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#define NVOBJ_ENGINE_COPY1 4
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#define NVOBJ_ENGINE_DISPLAY 15
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#define NVOBJ_ENGINE_NR 16
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@ -1137,6 +1139,7 @@ extern void nv40_grctx_init(struct nouveau_grctx *);
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extern int nv50_graph_create(struct drm_device *);
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extern int nv50_grctx_init(struct nouveau_grctx *);
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extern struct nouveau_enum nv50_data_error_names[];
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extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
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/* nvc0_graph.c */
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extern int nvc0_graph_create(struct drm_device *);
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@ -1144,6 +1147,12 @@ extern int nvc0_graph_create(struct drm_device *);
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/* nv84_crypt.c */
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extern int nv84_crypt_create(struct drm_device *);
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/* nva3_copy.c */
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extern int nva3_copy_create(struct drm_device *dev);
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/* nvc0_copy.c */
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extern int nvc0_copy_create(struct drm_device *dev, int engine);
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/* nv04_instmem.c */
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extern int nv04_instmem_init(struct drm_device *);
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extern void nv04_instmem_takedown(struct drm_device *);
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@ -598,6 +598,21 @@ nouveau_card_init(struct drm_device *dev)
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break;
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}
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switch (dev_priv->card_type) {
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case NV_50:
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switch (dev_priv->chipset) {
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case 0xa3:
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case 0xa5:
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case 0xa8:
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case 0xaf:
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nva3_copy_create(dev);
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break;
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}
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break;
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default:
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break;
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}
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if (!nouveau_noaccel) {
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for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
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if (dev_priv->eng[e]) {
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@ -939,7 +939,7 @@ nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid
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return 1;
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}
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static int
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int
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nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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226
drivers/gpu/drm/nouveau/nva3_copy.c
Normal file
226
drivers/gpu/drm/nouveau/nva3_copy.c
Normal file
@ -0,0 +1,226 @@
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/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <linux/firmware.h>
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_util.h"
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#include "nouveau_vm.h"
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#include "nouveau_ramht.h"
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#include "nva3_copy.fuc.h"
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struct nva3_copy_engine {
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struct nouveau_exec_engine base;
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};
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static int
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nva3_copy_context_new(struct nouveau_channel *chan, int engine)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramin = chan->ramin;
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struct nouveau_gpuobj *ctx = NULL;
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int ret;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &ctx);
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if (ret)
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return ret;
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nv_wo32(ramin, 0xc0, 0x00190000);
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nv_wo32(ramin, 0xc4, ctx->vinst + ctx->size - 1);
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nv_wo32(ramin, 0xc8, ctx->vinst);
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nv_wo32(ramin, 0xcc, 0x00000000);
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nv_wo32(ramin, 0xd0, 0x00000000);
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nv_wo32(ramin, 0xd4, 0x00000000);
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dev_priv->engine.instmem.flush(dev);
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atomic_inc(&chan->vm->engref[engine]);
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chan->engctx[engine] = ctx;
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return 0;
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}
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static int
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nva3_copy_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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struct nouveau_gpuobj *ctx = chan->engctx[engine];
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/* fuc engine doesn't need an object, our ramht code does.. */
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ctx->engine = 3;
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ctx->class = class;
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return nouveau_ramht_insert(chan, handle, ctx);
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}
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static void
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nva3_copy_context_del(struct nouveau_channel *chan, int engine)
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{
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struct nouveau_gpuobj *ctx = chan->engctx[engine];
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struct drm_device *dev = chan->dev;
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u32 inst;
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inst = (chan->ramin->vinst >> 12);
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inst |= 0x40000000;
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/* disable fifo access */
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nv_wr32(dev, 0x104048, 0x00000000);
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/* mark channel as unloaded if it's currently active */
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if (nv_rd32(dev, 0x104050) == inst)
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nv_mask(dev, 0x104050, 0x40000000, 0x00000000);
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/* mark next channel as invalid if it's about to be loaded */
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if (nv_rd32(dev, 0x104054) == inst)
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nv_mask(dev, 0x104054, 0x40000000, 0x00000000);
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/* restore fifo access */
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nv_wr32(dev, 0x104048, 0x00000003);
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for (inst = 0xc0; inst <= 0xd4; inst += 4)
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nv_wo32(chan->ramin, inst, 0x00000000);
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nouveau_gpuobj_ref(NULL, &ctx);
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atomic_dec(&chan->vm->engref[engine]);
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chan->engctx[engine] = ctx;
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}
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static void
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nva3_copy_tlb_flush(struct drm_device *dev, int engine)
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{
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nv50_vm_flush_engine(dev, 0x0d);
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}
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static int
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nva3_copy_init(struct drm_device *dev, int engine)
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{
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int i;
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nv_mask(dev, 0x000200, 0x00002000, 0x00000000);
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nv_mask(dev, 0x000200, 0x00002000, 0x00002000);
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nv_wr32(dev, 0x104014, 0xffffffff); /* disable all interrupts */
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/* upload ucode */
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nv_wr32(dev, 0x1041c0, 0x01000000);
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for (i = 0; i < sizeof(nva3_pcopy_data) / 4; i++)
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nv_wr32(dev, 0x1041c4, nva3_pcopy_data[i]);
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nv_wr32(dev, 0x104180, 0x01000000);
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for (i = 0; i < sizeof(nva3_pcopy_code) / 4; i++) {
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if ((i & 0x3f) == 0)
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nv_wr32(dev, 0x104188, i >> 6);
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nv_wr32(dev, 0x104184, nva3_pcopy_code[i]);
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}
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/* start it running */
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nv_wr32(dev, 0x10410c, 0x00000000);
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nv_wr32(dev, 0x104104, 0x00000000); /* ENTRY */
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nv_wr32(dev, 0x104100, 0x00000002); /* TRIGGER */
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return 0;
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}
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static int
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nva3_copy_fini(struct drm_device *dev, int engine)
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{
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nv_mask(dev, 0x104048, 0x00000003, 0x00000000);
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/* trigger fuc context unload */
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nv_wait(dev, 0x104008, 0x0000000c, 0x00000000);
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nv_mask(dev, 0x104054, 0x40000000, 0x00000000);
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nv_wr32(dev, 0x104000, 0x00000008);
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nv_wait(dev, 0x104008, 0x00000008, 0x00000000);
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nv_wr32(dev, 0x104014, 0xffffffff);
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return 0;
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}
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static struct nouveau_enum nva3_copy_isr_error_name[] = {
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{ 0x0001, "ILLEGAL_MTHD" },
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{ 0x0002, "INVALID_ENUM" },
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{ 0x0003, "INVALID_BITFIELD" },
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{}
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};
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static void
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nva3_copy_isr(struct drm_device *dev)
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{
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u32 dispatch = nv_rd32(dev, 0x10401c);
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u32 stat = nv_rd32(dev, 0x104008) & dispatch & ~(dispatch >> 16);
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u32 inst = nv_rd32(dev, 0x104050) & 0x3fffffff;
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u32 ssta = nv_rd32(dev, 0x104040) & 0x0000ffff;
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u32 addr = nv_rd32(dev, 0x104040) >> 16;
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u32 mthd = (addr & 0x07ff) << 2;
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u32 subc = (addr & 0x3800) >> 11;
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u32 data = nv_rd32(dev, 0x104044);
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int chid = nv50_graph_isr_chid(dev, inst);
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if (stat & 0x00000040) {
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NV_INFO(dev, "PCOPY: DISPATCH_ERROR [");
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nouveau_enum_print(nva3_copy_isr_error_name, ssta);
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printk("] ch %d [0x%08x] subc %d mthd 0x%04x data 0x%08x\n",
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chid, inst, subc, mthd, data);
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nv_wr32(dev, 0x104004, 0x00000040);
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stat &= ~0x00000040;
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}
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if (stat) {
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NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);
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nv_wr32(dev, 0x104004, stat);
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}
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nv50_fb_vm_trap(dev, 1);
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}
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static void
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nva3_copy_destroy(struct drm_device *dev, int engine)
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{
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struct nva3_copy_engine *pcopy = nv_engine(dev, engine);
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nouveau_irq_unregister(dev, 22);
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NVOBJ_ENGINE_DEL(dev, COPY0);
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kfree(pcopy);
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}
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int
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nva3_copy_create(struct drm_device *dev)
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{
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struct nva3_copy_engine *pcopy;
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pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL);
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if (!pcopy)
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return -ENOMEM;
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pcopy->base.destroy = nva3_copy_destroy;
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pcopy->base.init = nva3_copy_init;
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pcopy->base.fini = nva3_copy_fini;
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pcopy->base.context_new = nva3_copy_context_new;
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pcopy->base.context_del = nva3_copy_context_del;
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pcopy->base.object_new = nva3_copy_object_new;
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pcopy->base.tlb_flush = nva3_copy_tlb_flush;
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nouveau_irq_register(dev, 22, nva3_copy_isr);
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NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
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NVOBJ_CLASS(dev, 0x85b5, COPY0);
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return 0;
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}
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870
drivers/gpu/drm/nouveau/nva3_copy.fuc
Normal file
870
drivers/gpu/drm/nouveau/nva3_copy.fuc
Normal file
@ -0,0 +1,870 @@
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/* fuc microcode for copy engine on nva3- chipsets
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*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
|
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*
|
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
|
||||
*
|
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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/* To build for nva3:nvc0
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* m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h
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*
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* To build for nvc0-
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* m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h
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*/
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ifdef(`NVA3',
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.section nva3_pcopy_data,
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.section nvc0_pcopy_data
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)
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ctx_object: .b32 0
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ifdef(`NVA3',
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ctx_dma:
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ctx_dma_query: .b32 0
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ctx_dma_src: .b32 0
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ctx_dma_dst: .b32 0
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,)
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.equ ctx_dma_count 3
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ctx_query_address_high: .b32 0
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ctx_query_address_low: .b32 0
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ctx_query_counter: .b32 0
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ctx_src_address_high: .b32 0
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ctx_src_address_low: .b32 0
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ctx_src_pitch: .b32 0
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ctx_src_tile_mode: .b32 0
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ctx_src_xsize: .b32 0
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ctx_src_ysize: .b32 0
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ctx_src_zsize: .b32 0
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ctx_src_zoff: .b32 0
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ctx_src_xoff: .b32 0
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ctx_src_yoff: .b32 0
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ctx_src_cpp: .b32 0
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ctx_dst_address_high: .b32 0
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ctx_dst_address_low: .b32 0
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ctx_dst_pitch: .b32 0
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ctx_dst_tile_mode: .b32 0
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ctx_dst_xsize: .b32 0
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ctx_dst_ysize: .b32 0
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ctx_dst_zsize: .b32 0
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ctx_dst_zoff: .b32 0
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ctx_dst_xoff: .b32 0
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ctx_dst_yoff: .b32 0
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ctx_dst_cpp: .b32 0
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ctx_format: .b32 0
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ctx_swz_const0: .b32 0
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ctx_swz_const1: .b32 0
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ctx_xcnt: .b32 0
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ctx_ycnt: .b32 0
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.align 256
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dispatch_table:
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// mthd 0x0000, NAME
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.b16 0x000 1
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.b32 ctx_object ~0xffffffff
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// mthd 0x0100, NOP
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.b16 0x040 1
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.b32 0x00010000 + cmd_nop ~0xffffffff
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// mthd 0x0140, PM_TRIGGER
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.b16 0x050 1
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.b32 0x00010000 + cmd_pm_trigger ~0xffffffff
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ifdef(`NVA3', `
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// mthd 0x0180-0x018c, DMA_
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.b16 0x060 ctx_dma_count
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dispatch_dma:
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.b32 0x00010000 + cmd_dma ~0xffffffff
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.b32 0x00010000 + cmd_dma ~0xffffffff
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.b32 0x00010000 + cmd_dma ~0xffffffff
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',)
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// mthd 0x0200-0x0218, SRC_TILE
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.b16 0x80 7
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.b32 ctx_src_tile_mode ~0x00000fff
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.b32 ctx_src_xsize ~0x0007ffff
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.b32 ctx_src_ysize ~0x00001fff
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.b32 ctx_src_zsize ~0x000007ff
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.b32 ctx_src_zoff ~0x00000fff
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.b32 ctx_src_xoff ~0x0007ffff
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.b32 ctx_src_yoff ~0x00001fff
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// mthd 0x0220-0x0238, DST_TILE
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.b16 0x88 7
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.b32 ctx_dst_tile_mode ~0x00000fff
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.b32 ctx_dst_xsize ~0x0007ffff
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.b32 ctx_dst_ysize ~0x00001fff
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.b32 ctx_dst_zsize ~0x000007ff
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.b32 ctx_dst_zoff ~0x00000fff
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.b32 ctx_dst_xoff ~0x0007ffff
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.b32 ctx_dst_yoff ~0x00001fff
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// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH
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.b16 0xc0 2
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.b32 0x00010000 + cmd_exec ~0xffffffff
|
||||
.b32 0x00010000 + cmd_wrcache_flush ~0xffffffff
|
||||
// mthd 0x030c-0x0340, various stuff
|
||||
.b16 0xc3 14
|
||||
.b32 ctx_src_address_high ~0x000000ff
|
||||
.b32 ctx_src_address_low ~0xfffffff0
|
||||
.b32 ctx_dst_address_high ~0x000000ff
|
||||
.b32 ctx_dst_address_low ~0xfffffff0
|
||||
.b32 ctx_src_pitch ~0x0007ffff
|
||||
.b32 ctx_dst_pitch ~0x0007ffff
|
||||
.b32 ctx_xcnt ~0x0000ffff
|
||||
.b32 ctx_ycnt ~0x00001fff
|
||||
.b32 ctx_format ~0x0333ffff
|
||||
.b32 ctx_swz_const0 ~0xffffffff
|
||||
.b32 ctx_swz_const1 ~0xffffffff
|
||||
.b32 ctx_query_address_high ~0x000000ff
|
||||
.b32 ctx_query_address_low ~0xffffffff
|
||||
.b32 ctx_query_counter ~0xffffffff
|
||||
.b16 0x800 0
|
||||
|
||||
ifdef(`NVA3',
|
||||
.section nva3_pcopy_code,
|
||||
.section nvc0_pcopy_code
|
||||
)
|
||||
|
||||
main:
|
||||
clear b32 $r0
|
||||
mov $sp $r0
|
||||
|
||||
// setup i0 handler and route fifo and ctxswitch to it
|
||||
mov $r1 ih
|
||||
mov $iv0 $r1
|
||||
mov $r1 0x400
|
||||
movw $r2 0xfff3
|
||||
sethi $r2 0
|
||||
iowr I[$r2 + 0x300] $r2
|
||||
|
||||
// enable interrupts
|
||||
or $r2 0xc
|
||||
iowr I[$r1] $r2
|
||||
bset $flags ie0
|
||||
|
||||
// enable fifo access and context switching
|
||||
mov $r1 0x1200
|
||||
mov $r2 3
|
||||
iowr I[$r1] $r2
|
||||
|
||||
// sleep forever, waking for interrupts
|
||||
bset $flags $p0
|
||||
spin:
|
||||
sleep $p0
|
||||
bra spin
|
||||
|
||||
// i0 handler
|
||||
ih:
|
||||
iord $r1 I[$r0 + 0x200]
|
||||
|
||||
and $r2 $r1 0x00000008
|
||||
bra e ih_no_chsw
|
||||
call chsw
|
||||
ih_no_chsw:
|
||||
and $r2 $r1 0x00000004
|
||||
bra e ih_no_cmd
|
||||
call dispatch
|
||||
|
||||
ih_no_cmd:
|
||||
and $r1 $r1 0x0000000c
|
||||
iowr I[$r0 + 0x100] $r1
|
||||
iret
|
||||
|
||||
// $p1 direction (0 = unload, 1 = load)
|
||||
// $r3 channel
|
||||
swctx:
|
||||
mov $r4 0x7700
|
||||
mov $xtargets $r4
|
||||
ifdef(`NVA3', `
|
||||
// target 7 hardcoded to ctx dma object
|
||||
mov $xdbase $r0
|
||||
', ` // NVC0
|
||||
// read SCRATCH3 to decide if we are PCOPY0 or PCOPY1
|
||||
mov $r4 0x2100
|
||||
iord $r4 I[$r4 + 0]
|
||||
and $r4 1
|
||||
shl b32 $r4 4
|
||||
add b32 $r4 0x30
|
||||
|
||||
// channel is in vram
|
||||
mov $r15 0x61c
|
||||
shl b32 $r15 6
|
||||
mov $r5 0x114
|
||||
iowrs I[$r15] $r5
|
||||
|
||||
// read 16-byte PCOPYn info, containing context pointer, from channel
|
||||
shl b32 $r5 $r3 4
|
||||
add b32 $r5 2
|
||||
mov $xdbase $r5
|
||||
mov $r5 $sp
|
||||
// get a chunk of stack space, aligned to 256 byte boundary
|
||||
sub b32 $r5 0x100
|
||||
mov $r6 0xff
|
||||
not b32 $r6
|
||||
and $r5 $r6
|
||||
sethi $r5 0x00020000
|
||||
xdld $r4 $r5
|
||||
xdwait
|
||||
sethi $r5 0
|
||||
|
||||
// set context pointer, from within channel VM
|
||||
mov $r14 0
|
||||
iowrs I[$r15] $r14
|
||||
ld b32 $r4 D[$r5 + 0]
|
||||
shr b32 $r4 8
|
||||
ld b32 $r6 D[$r5 + 4]
|
||||
shl b32 $r6 24
|
||||
or $r4 $r6
|
||||
mov $xdbase $r4
|
||||
')
|
||||
// 256-byte context, at start of data segment
|
||||
mov b32 $r4 $r0
|
||||
sethi $r4 0x60000
|
||||
|
||||
// swap!
|
||||
bra $p1 swctx_load
|
||||
xdst $r0 $r4
|
||||
bra swctx_done
|
||||
swctx_load:
|
||||
xdld $r0 $r4
|
||||
swctx_done:
|
||||
xdwait
|
||||
ret
|
||||
|
||||
chsw:
|
||||
// read current channel
|
||||
mov $r2 0x1400
|
||||
iord $r3 I[$r2]
|
||||
|
||||
// if it's active, unload it and return
|
||||
xbit $r15 $r3 0x1e
|
||||
bra e chsw_no_unload
|
||||
bclr $flags $p1
|
||||
call swctx
|
||||
bclr $r3 0x1e
|
||||
iowr I[$r2] $r3
|
||||
mov $r4 1
|
||||
iowr I[$r2 + 0x200] $r4
|
||||
ret
|
||||
|
||||
// read next channel
|
||||
chsw_no_unload:
|
||||
iord $r3 I[$r2 + 0x100]
|
||||
|
||||
// is there a channel waiting to be loaded?
|
||||
xbit $r13 $r3 0x1e
|
||||
bra e chsw_finish_load
|
||||
bset $flags $p1
|
||||
call swctx
|
||||
ifdef(`NVA3',
|
||||
// load dma objects back into TARGET regs
|
||||
mov $r5 ctx_dma
|
||||
mov $r6 ctx_dma_count
|
||||
chsw_load_ctx_dma:
|
||||
ld b32 $r7 D[$r5 + $r6 * 4]
|
||||
add b32 $r8 $r6 0x180
|
||||
shl b32 $r8 8
|
||||
iowr I[$r8] $r7
|
||||
sub b32 $r6 1
|
||||
bra nc chsw_load_ctx_dma
|
||||
,)
|
||||
|
||||
chsw_finish_load:
|
||||
mov $r3 2
|
||||
iowr I[$r2 + 0x200] $r3
|
||||
ret
|
||||
|
||||
dispatch:
|
||||
// read incoming fifo command
|
||||
mov $r3 0x1900
|
||||
iord $r2 I[$r3 + 0x100]
|
||||
iord $r3 I[$r3 + 0x000]
|
||||
and $r4 $r2 0x7ff
|
||||
// $r2 will be used to store exception data
|
||||
shl b32 $r2 0x10
|
||||
|
||||
// lookup method in the dispatch table, ILLEGAL_MTHD if not found
|
||||
mov $r5 dispatch_table
|
||||
clear b32 $r6
|
||||
clear b32 $r7
|
||||
dispatch_loop:
|
||||
ld b16 $r6 D[$r5 + 0]
|
||||
ld b16 $r7 D[$r5 + 2]
|
||||
add b32 $r5 4
|
||||
cmpu b32 $r4 $r6
|
||||
bra c dispatch_illegal_mthd
|
||||
add b32 $r7 $r6
|
||||
cmpu b32 $r4 $r7
|
||||
bra c dispatch_valid_mthd
|
||||
sub b32 $r7 $r6
|
||||
shl b32 $r7 3
|
||||
add b32 $r5 $r7
|
||||
bra dispatch_loop
|
||||
|
||||
// ensure no bits set in reserved fields, INVALID_BITFIELD
|
||||
dispatch_valid_mthd:
|
||||
sub b32 $r4 $r6
|
||||
shl b32 $r4 3
|
||||
add b32 $r4 $r5
|
||||
ld b32 $r5 D[$r4 + 4]
|
||||
and $r5 $r3
|
||||
cmpu b32 $r5 0
|
||||
bra ne dispatch_invalid_bitfield
|
||||
|
||||
// depending on dispatch flags: execute method, or save data as state
|
||||
ld b16 $r5 D[$r4 + 0]
|
||||
ld b16 $r6 D[$r4 + 2]
|
||||
cmpu b32 $r6 0
|
||||
bra ne dispatch_cmd
|
||||
st b32 D[$r5] $r3
|
||||
bra dispatch_done
|
||||
dispatch_cmd:
|
||||
bclr $flags $p1
|
||||
call $r5
|
||||
bra $p1 dispatch_error
|
||||
bra dispatch_done
|
||||
|
||||
dispatch_invalid_bitfield:
|
||||
or $r2 2
|
||||
dispatch_illegal_mthd:
|
||||
or $r2 1
|
||||
|
||||
// store exception data in SCRATCH0/SCRATCH1, signal hostirq
|
||||
dispatch_error:
|
||||
mov $r4 0x1000
|
||||
iowr I[$r4 + 0x000] $r2
|
||||
iowr I[$r4 + 0x100] $r3
|
||||
mov $r2 0x40
|
||||
iowr I[$r0] $r2
|
||||
hostirq_wait:
|
||||
iord $r2 I[$r0 + 0x200]
|
||||
and $r2 0x40
|
||||
cmpu b32 $r2 0
|
||||
bra ne hostirq_wait
|
||||
|
||||
dispatch_done:
|
||||
mov $r2 0x1d00
|
||||
mov $r3 1
|
||||
iowr I[$r2] $r3
|
||||
ret
|
||||
|
||||
// No-operation
|
||||
//
|
||||
// Inputs:
|
||||
// $r1: irqh state
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
// $r4: dispatch table entry
|
||||
// Outputs:
|
||||
// $r1: irqh state
|
||||
// $p1: set on error
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
cmd_nop:
|
||||
ret
|
||||
|
||||
// PM_TRIGGER
|
||||
//
|
||||
// Inputs:
|
||||
// $r1: irqh state
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
// $r4: dispatch table entry
|
||||
// Outputs:
|
||||
// $r1: irqh state
|
||||
// $p1: set on error
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
cmd_pm_trigger:
|
||||
mov $r2 0x2200
|
||||
clear b32 $r3
|
||||
sethi $r3 0x20000
|
||||
iowr I[$r2] $r3
|
||||
ret
|
||||
|
||||
ifdef(`NVA3',
|
||||
// SET_DMA_* method handler
|
||||
//
|
||||
// Inputs:
|
||||
// $r1: irqh state
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
// $r4: dispatch table entry
|
||||
// Outputs:
|
||||
// $r1: irqh state
|
||||
// $p1: set on error
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
cmd_dma:
|
||||
sub b32 $r4 dispatch_dma
|
||||
shr b32 $r4 1
|
||||
bset $r3 0x1e
|
||||
st b32 D[$r4 + ctx_dma] $r3
|
||||
add b32 $r4 0x600
|
||||
shl b32 $r4 6
|
||||
iowr I[$r4] $r3
|
||||
ret
|
||||
,)
|
||||
|
||||
// Calculates the hw swizzle mask and adjusts the surface's xcnt to match
|
||||
//
|
||||
cmd_exec_set_format:
|
||||
// zero out a chunk of the stack to store the swizzle into
|
||||
add $sp -0x10
|
||||
st b32 D[$sp + 0x00] $r0
|
||||
st b32 D[$sp + 0x04] $r0
|
||||
st b32 D[$sp + 0x08] $r0
|
||||
st b32 D[$sp + 0x0c] $r0
|
||||
|
||||
// extract cpp, src_ncomp and dst_ncomp from FORMAT
|
||||
ld b32 $r4 D[$r0 + ctx_format]
|
||||
extr $r5 $r4 16:17
|
||||
add b32 $r5 1
|
||||
extr $r6 $r4 20:21
|
||||
add b32 $r6 1
|
||||
extr $r7 $r4 24:25
|
||||
add b32 $r7 1
|
||||
|
||||
// convert FORMAT swizzle mask to hw swizzle mask
|
||||
bclr $flags $p2
|
||||
clear b32 $r8
|
||||
clear b32 $r9
|
||||
ncomp_loop:
|
||||
and $r10 $r4 0xf
|
||||
shr b32 $r4 4
|
||||
clear b32 $r11
|
||||
bpc_loop:
|
||||
cmpu b8 $r10 4
|
||||
bra nc cmp_c0
|
||||
mulu $r12 $r10 $r5
|
||||
add b32 $r12 $r11
|
||||
bset $flags $p2
|
||||
bra bpc_next
|
||||
cmp_c0:
|
||||
bra ne cmp_c1
|
||||
mov $r12 0x10
|
||||
add b32 $r12 $r11
|
||||
bra bpc_next
|
||||
cmp_c1:
|
||||
cmpu b8 $r10 6
|
||||
bra nc cmp_zero
|
||||
mov $r12 0x14
|
||||
add b32 $r12 $r11
|
||||
bra bpc_next
|
||||
cmp_zero:
|
||||
mov $r12 0x80
|
||||
bpc_next:
|
||||
st b8 D[$sp + $r8] $r12
|
||||
add b32 $r8 1
|
||||
add b32 $r11 1
|
||||
cmpu b32 $r11 $r5
|
||||
bra c bpc_loop
|
||||
add b32 $r9 1
|
||||
cmpu b32 $r9 $r7
|
||||
bra c ncomp_loop
|
||||
|
||||
// SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang)
|
||||
mulu $r6 $r5
|
||||
st b32 D[$r0 + ctx_src_cpp] $r6
|
||||
ld b32 $r8 D[$r0 + ctx_xcnt]
|
||||
mulu $r6 $r8
|
||||
bra $p2 dst_xcnt
|
||||
clear b32 $r6
|
||||
|
||||
dst_xcnt:
|
||||
mulu $r7 $r5
|
||||
st b32 D[$r0 + ctx_dst_cpp] $r7
|
||||
mulu $r7 $r8
|
||||
|
||||
mov $r5 0x810
|
||||
shl b32 $r5 6
|
||||
iowr I[$r5 + 0x000] $r6
|
||||
iowr I[$r5 + 0x100] $r7
|
||||
add b32 $r5 0x800
|
||||
ld b32 $r6 D[$r0 + ctx_dst_cpp]
|
||||
sub b32 $r6 1
|
||||
shl b32 $r6 8
|
||||
ld b32 $r7 D[$r0 + ctx_src_cpp]
|
||||
sub b32 $r7 1
|
||||
or $r6 $r7
|
||||
iowr I[$r5 + 0x000] $r6
|
||||
add b32 $r5 0x100
|
||||
ld b32 $r6 D[$sp + 0x00]
|
||||
iowr I[$r5 + 0x000] $r6
|
||||
ld b32 $r6 D[$sp + 0x04]
|
||||
iowr I[$r5 + 0x100] $r6
|
||||
ld b32 $r6 D[$sp + 0x08]
|
||||
iowr I[$r5 + 0x200] $r6
|
||||
ld b32 $r6 D[$sp + 0x0c]
|
||||
iowr I[$r5 + 0x300] $r6
|
||||
add b32 $r5 0x400
|
||||
ld b32 $r6 D[$r0 + ctx_swz_const0]
|
||||
iowr I[$r5 + 0x000] $r6
|
||||
ld b32 $r6 D[$r0 + ctx_swz_const1]
|
||||
iowr I[$r5 + 0x100] $r6
|
||||
add $sp 0x10
|
||||
ret
|
||||
|
||||
// Setup to handle a tiled surface
|
||||
//
|
||||
// Calculates a number of parameters the hardware requires in order
|
||||
// to correctly handle tiling.
|
||||
//
|
||||
// Offset calculation is performed as follows (Tp/Th/Td from TILE_MODE):
|
||||
// nTx = round_up(w * cpp, 1 << Tp) >> Tp
|
||||
// nTy = round_up(h, 1 << Th) >> Th
|
||||
// Txo = (x * cpp) & ((1 << Tp) - 1)
|
||||
// Tx = (x * cpp) >> Tp
|
||||
// Tyo = y & ((1 << Th) - 1)
|
||||
// Ty = y >> Th
|
||||
// Tzo = z & ((1 << Td) - 1)
|
||||
// Tz = z >> Td
|
||||
//
|
||||
// off = (Tzo << Tp << Th) + (Tyo << Tp) + Txo
|
||||
// off += ((Tz * nTy * nTx)) + (Ty * nTx) + Tx) << Td << Th << Tp;
|
||||
//
|
||||
// Inputs:
|
||||
// $r4: hw command (0x104800)
|
||||
// $r5: ctx offset adjustment for src/dst selection
|
||||
// $p2: set if dst surface
|
||||
//
|
||||
cmd_exec_set_surface_tiled:
|
||||
// translate TILE_MODE into Tp, Th, Td shift values
|
||||
ld b32 $r7 D[$r5 + ctx_src_tile_mode]
|
||||
extr $r9 $r7 8:11
|
||||
extr $r8 $r7 4:7
|
||||
ifdef(`NVA3',
|
||||
add b32 $r8 2
|
||||
,
|
||||
add b32 $r8 3
|
||||
)
|
||||
extr $r7 $r7 0:3
|
||||
cmp b32 $r7 0xe
|
||||
bra ne xtile64
|
||||
mov $r7 4
|
||||
bra xtileok
|
||||
xtile64:
|
||||
xbit $r7 $flags $p2
|
||||
add b32 $r7 17
|
||||
bset $r4 $r7
|
||||
mov $r7 6
|
||||
xtileok:
|
||||
|
||||
// Op = (x * cpp) & ((1 << Tp) - 1)
|
||||
// Tx = (x * cpp) >> Tp
|
||||
ld b32 $r10 D[$r5 + ctx_src_xoff]
|
||||
ld b32 $r11 D[$r5 + ctx_src_cpp]
|
||||
mulu $r10 $r11
|
||||
mov $r11 1
|
||||
shl b32 $r11 $r7
|
||||
sub b32 $r11 1
|
||||
and $r12 $r10 $r11
|
||||
shr b32 $r10 $r7
|
||||
|
||||
// Tyo = y & ((1 << Th) - 1)
|
||||
// Ty = y >> Th
|
||||
ld b32 $r13 D[$r5 + ctx_src_yoff]
|
||||
mov $r14 1
|
||||
shl b32 $r14 $r8
|
||||
sub b32 $r14 1
|
||||
and $r11 $r13 $r14
|
||||
shr b32 $r13 $r8
|
||||
|
||||
// YTILE = ((1 << Th) << 12) | ((1 << Th) - Tyo)
|
||||
add b32 $r14 1
|
||||
shl b32 $r15 $r14 12
|
||||
sub b32 $r14 $r11
|
||||
or $r15 $r14
|
||||
xbit $r6 $flags $p2
|
||||
add b32 $r6 0x208
|
||||
shl b32 $r6 8
|
||||
iowr I[$r6 + 0x000] $r15
|
||||
|
||||
// Op += Tyo << Tp
|
||||
shl b32 $r11 $r7
|
||||
add b32 $r12 $r11
|
||||
|
||||
// nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp)
|
||||
ld b32 $r15 D[$r5 + ctx_src_xsize]
|
||||
ld b32 $r11 D[$r5 + ctx_src_cpp]
|
||||
mulu $r15 $r11
|
||||
mov $r11 1
|
||||
shl b32 $r11 $r7
|
||||
sub b32 $r11 1
|
||||
add b32 $r15 $r11
|
||||
shr b32 $r15 $r7
|
||||
push $r15
|
||||
|
||||
// nTy = (h + ((1 << Th) - 1)) >> Th
|
||||
ld b32 $r15 D[$r5 + ctx_src_ysize]
|
||||
mov $r11 1
|
||||
shl b32 $r11 $r8
|
||||
sub b32 $r11 1
|
||||
add b32 $r15 $r11
|
||||
shr b32 $r15 $r8
|
||||
push $r15
|
||||
|
||||
// Tys = Tp + Th
|
||||
// CFG_YZ_TILE_SIZE = ((1 << Th) >> 2) << Td
|
||||
add b32 $r7 $r8
|
||||
sub b32 $r8 2
|
||||
mov $r11 1
|
||||
shl b32 $r11 $r8
|
||||
shl b32 $r11 $r9
|
||||
|
||||
// Tzo = z & ((1 << Td) - 1)
|
||||
// Tz = z >> Td
|
||||
// Op += Tzo << Tys
|
||||
// Ts = Tys + Td
|
||||
ld b32 $r8 D[$r5 + ctx_src_zoff]
|
||||
mov $r14 1
|
||||
shl b32 $r14 $r9
|
||||
sub b32 $r14 1
|
||||
and $r15 $r8 $r14
|
||||
shl b32 $r15 $r7
|
||||
add b32 $r12 $r15
|
||||
add b32 $r7 $r9
|
||||
shr b32 $r8 $r9
|
||||
|
||||
// Ot = ((Tz * nTy * nTx) + (Ty * nTx) + Tx) << Ts
|
||||
pop $r15
|
||||
pop $r9
|
||||
mulu $r13 $r9
|
||||
add b32 $r10 $r13
|
||||
mulu $r8 $r9
|
||||
mulu $r8 $r15
|
||||
add b32 $r10 $r8
|
||||
shl b32 $r10 $r7
|
||||
|
||||
// PITCH = (nTx - 1) << Ts
|
||||
sub b32 $r9 1
|
||||
shl b32 $r9 $r7
|
||||
iowr I[$r6 + 0x200] $r9
|
||||
|
||||
// SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff
|
||||
// CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16
|
||||
ld b32 $r7 D[$r5 + ctx_src_address_low]
|
||||
ld b32 $r8 D[$r5 + ctx_src_address_high]
|
||||
add b32 $r10 $r12
|
||||
add b32 $r7 $r10
|
||||
adc b32 $r8 0
|
||||
shl b32 $r8 16
|
||||
or $r8 $r11
|
||||
sub b32 $r6 0x600
|
||||
iowr I[$r6 + 0x000] $r7
|
||||
add b32 $r6 0x400
|
||||
iowr I[$r6 + 0x000] $r8
|
||||
ret
|
||||
|
||||
// Setup to handle a linear surface
|
||||
//
|
||||
// Nothing to see here.. Sets ADDRESS and PITCH, pretty non-exciting
|
||||
//
|
||||
cmd_exec_set_surface_linear:
|
||||
xbit $r6 $flags $p2
|
||||
add b32 $r6 0x202
|
||||
shl b32 $r6 8
|
||||
ld b32 $r7 D[$r5 + ctx_src_address_low]
|
||||
iowr I[$r6 + 0x000] $r7
|
||||
add b32 $r6 0x400
|
||||
ld b32 $r7 D[$r5 + ctx_src_address_high]
|
||||
shl b32 $r7 16
|
||||
iowr I[$r6 + 0x000] $r7
|
||||
add b32 $r6 0x400
|
||||
ld b32 $r7 D[$r5 + ctx_src_pitch]
|
||||
iowr I[$r6 + 0x000] $r7
|
||||
ret
|
||||
|
||||
// wait for regs to be available for use
|
||||
cmd_exec_wait:
|
||||
push $r0
|
||||
push $r1
|
||||
mov $r0 0x800
|
||||
shl b32 $r0 6
|
||||
loop:
|
||||
iord $r1 I[$r0]
|
||||
and $r1 1
|
||||
bra ne loop
|
||||
pop $r1
|
||||
pop $r0
|
||||
ret
|
||||
|
||||
cmd_exec_query:
|
||||
// if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI }
|
||||
xbit $r4 $r3 13
|
||||
bra ne query_counter
|
||||
call cmd_exec_wait
|
||||
mov $r4 0x80c
|
||||
shl b32 $r4 6
|
||||
ld b32 $r5 D[$r0 + ctx_query_address_low]
|
||||
add b32 $r5 4
|
||||
iowr I[$r4 + 0x000] $r5
|
||||
iowr I[$r4 + 0x100] $r0
|
||||
mov $r5 0xc
|
||||
iowr I[$r4 + 0x200] $r5
|
||||
add b32 $r4 0x400
|
||||
ld b32 $r5 D[$r0 + ctx_query_address_high]
|
||||
shl b32 $r5 16
|
||||
iowr I[$r4 + 0x000] $r5
|
||||
add b32 $r4 0x500
|
||||
mov $r5 0x00000b00
|
||||
sethi $r5 0x00010000
|
||||
iowr I[$r4 + 0x000] $r5
|
||||
mov $r5 0x00004040
|
||||
shl b32 $r5 1
|
||||
sethi $r5 0x80800000
|
||||
iowr I[$r4 + 0x100] $r5
|
||||
mov $r5 0x00001110
|
||||
sethi $r5 0x13120000
|
||||
iowr I[$r4 + 0x200] $r5
|
||||
mov $r5 0x00001514
|
||||
sethi $r5 0x17160000
|
||||
iowr I[$r4 + 0x300] $r5
|
||||
mov $r5 0x00002601
|
||||
sethi $r5 0x00010000
|
||||
mov $r4 0x800
|
||||
shl b32 $r4 6
|
||||
iowr I[$r4 + 0x000] $r5
|
||||
|
||||
// write COUNTER
|
||||
query_counter:
|
||||
call cmd_exec_wait
|
||||
mov $r4 0x80c
|
||||
shl b32 $r4 6
|
||||
ld b32 $r5 D[$r0 + ctx_query_address_low]
|
||||
iowr I[$r4 + 0x000] $r5
|
||||
iowr I[$r4 + 0x100] $r0
|
||||
mov $r5 0x4
|
||||
iowr I[$r4 + 0x200] $r5
|
||||
add b32 $r4 0x400
|
||||
ld b32 $r5 D[$r0 + ctx_query_address_high]
|
||||
shl b32 $r5 16
|
||||
iowr I[$r4 + 0x000] $r5
|
||||
add b32 $r4 0x500
|
||||
mov $r5 0x00000300
|
||||
iowr I[$r4 + 0x000] $r5
|
||||
mov $r5 0x00001110
|
||||
sethi $r5 0x13120000
|
||||
iowr I[$r4 + 0x100] $r5
|
||||
ld b32 $r5 D[$r0 + ctx_query_counter]
|
||||
add b32 $r4 0x500
|
||||
iowr I[$r4 + 0x000] $r5
|
||||
mov $r5 0x00002601
|
||||
sethi $r5 0x00010000
|
||||
mov $r4 0x800
|
||||
shl b32 $r4 6
|
||||
iowr I[$r4 + 0x000] $r5
|
||||
ret
|
||||
|
||||
// Execute a copy operation
|
||||
//
|
||||
// Inputs:
|
||||
// $r1: irqh state
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
// 000002000 QUERY_SHORT
|
||||
// 000001000 QUERY
|
||||
// 000000100 DST_LINEAR
|
||||
// 000000010 SRC_LINEAR
|
||||
// 000000001 FORMAT
|
||||
// $r4: dispatch table entry
|
||||
// Outputs:
|
||||
// $r1: irqh state
|
||||
// $p1: set on error
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
cmd_exec:
|
||||
call cmd_exec_wait
|
||||
|
||||
// if format requested, call function to calculate it, otherwise
|
||||
// fill in cpp/xcnt for both surfaces as if (cpp == 1)
|
||||
xbit $r15 $r3 0
|
||||
bra e cmd_exec_no_format
|
||||
call cmd_exec_set_format
|
||||
mov $r4 0x200
|
||||
bra cmd_exec_init_src_surface
|
||||
cmd_exec_no_format:
|
||||
mov $r6 0x810
|
||||
shl b32 $r6 6
|
||||
mov $r7 1
|
||||
st b32 D[$r0 + ctx_src_cpp] $r7
|
||||
st b32 D[$r0 + ctx_dst_cpp] $r7
|
||||
ld b32 $r7 D[$r0 + ctx_xcnt]
|
||||
iowr I[$r6 + 0x000] $r7
|
||||
iowr I[$r6 + 0x100] $r7
|
||||
clear b32 $r4
|
||||
|
||||
cmd_exec_init_src_surface:
|
||||
bclr $flags $p2
|
||||
clear b32 $r5
|
||||
xbit $r15 $r3 4
|
||||
bra e src_tiled
|
||||
call cmd_exec_set_surface_linear
|
||||
bra cmd_exec_init_dst_surface
|
||||
src_tiled:
|
||||
call cmd_exec_set_surface_tiled
|
||||
bset $r4 7
|
||||
|
||||
cmd_exec_init_dst_surface:
|
||||
bset $flags $p2
|
||||
mov $r5 ctx_dst_address_high - ctx_src_address_high
|
||||
xbit $r15 $r3 8
|
||||
bra e dst_tiled
|
||||
call cmd_exec_set_surface_linear
|
||||
bra cmd_exec_kick
|
||||
dst_tiled:
|
||||
call cmd_exec_set_surface_tiled
|
||||
bset $r4 8
|
||||
|
||||
cmd_exec_kick:
|
||||
mov $r5 0x800
|
||||
shl b32 $r5 6
|
||||
ld b32 $r6 D[$r0 + ctx_ycnt]
|
||||
iowr I[$r5 + 0x100] $r6
|
||||
mov $r6 0x0041
|
||||
// SRC_TARGET = 1, DST_TARGET = 2
|
||||
sethi $r6 0x44000000
|
||||
or $r4 $r6
|
||||
iowr I[$r5] $r4
|
||||
|
||||
// if requested, queue up a QUERY write after the copy has completed
|
||||
xbit $r15 $r3 12
|
||||
bra e cmd_exec_done
|
||||
call cmd_exec_query
|
||||
|
||||
cmd_exec_done:
|
||||
ret
|
||||
|
||||
// Flush write cache
|
||||
//
|
||||
// Inputs:
|
||||
// $r1: irqh state
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
// $r4: dispatch table entry
|
||||
// Outputs:
|
||||
// $r1: irqh state
|
||||
// $p1: set on error
|
||||
// $r2: hostirq state
|
||||
// $r3: data
|
||||
cmd_wrcache_flush:
|
||||
mov $r2 0x2200
|
||||
clear b32 $r3
|
||||
sethi $r3 0x10000
|
||||
iowr I[$r2] $r3
|
||||
ret
|
||||
|
||||
.align 0x100
|
||||
534
drivers/gpu/drm/nouveau/nva3_copy.fuc.h
Normal file
534
drivers/gpu/drm/nouveau/nva3_copy.fuc.h
Normal file
@ -0,0 +1,534 @@
|
||||
uint32_t nva3_pcopy_data[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00010000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00010040,
|
||||
0x00010160,
|
||||
0x00000000,
|
||||
0x00010050,
|
||||
0x00010162,
|
||||
0x00000000,
|
||||
0x00030060,
|
||||
0x00010170,
|
||||
0x00000000,
|
||||
0x00010170,
|
||||
0x00000000,
|
||||
0x00010170,
|
||||
0x00000000,
|
||||
0x00070080,
|
||||
0x00000028,
|
||||
0xfffff000,
|
||||
0x0000002c,
|
||||
0xfff80000,
|
||||
0x00000030,
|
||||
0xffffe000,
|
||||
0x00000034,
|
||||
0xfffff800,
|
||||
0x00000038,
|
||||
0xfffff000,
|
||||
0x0000003c,
|
||||
0xfff80000,
|
||||
0x00000040,
|
||||
0xffffe000,
|
||||
0x00070088,
|
||||
0x00000054,
|
||||
0xfffff000,
|
||||
0x00000058,
|
||||
0xfff80000,
|
||||
0x0000005c,
|
||||
0xffffe000,
|
||||
0x00000060,
|
||||
0xfffff800,
|
||||
0x00000064,
|
||||
0xfffff000,
|
||||
0x00000068,
|
||||
0xfff80000,
|
||||
0x0000006c,
|
||||
0xffffe000,
|
||||
0x000200c0,
|
||||
0x00010492,
|
||||
0x00000000,
|
||||
0x0001051b,
|
||||
0x00000000,
|
||||
0x000e00c3,
|
||||
0x0000001c,
|
||||
0xffffff00,
|
||||
0x00000020,
|
||||
0x0000000f,
|
||||
0x00000048,
|
||||
0xffffff00,
|
||||
0x0000004c,
|
||||
0x0000000f,
|
||||
0x00000024,
|
||||
0xfff80000,
|
||||
0x00000050,
|
||||
0xfff80000,
|
||||
0x00000080,
|
||||
0xffff0000,
|
||||
0x00000084,
|
||||
0xffffe000,
|
||||
0x00000074,
|
||||
0xfccc0000,
|
||||
0x00000078,
|
||||
0x00000000,
|
||||
0x0000007c,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0xffffff00,
|
||||
0x00000014,
|
||||
0x00000000,
|
||||
0x00000018,
|
||||
0x00000000,
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
uint32_t nva3_pcopy_code[] = {
|
||||
0x04fe04bd,
|
||||
0x3517f000,
|
||||
0xf10010fe,
|
||||
0xf1040017,
|
||||
0xf0fff327,
|
||||
0x22d00023,
|
||||
0x0c25f0c0,
|
||||
0xf40012d0,
|
||||
0x17f11031,
|
||||
0x27f01200,
|
||||
0x0012d003,
|
||||
0xf40031f4,
|
||||
0x0ef40028,
|
||||
0x8001cffd,
|
||||
0xf40812c4,
|
||||
0x21f4060b,
|
||||
0x0412c472,
|
||||
0xf4060bf4,
|
||||
0x11c4c321,
|
||||
0x4001d00c,
|
||||
0x47f101f8,
|
||||
0x4bfe7700,
|
||||
0x0007fe00,
|
||||
0xf00204b9,
|
||||
0x01f40643,
|
||||
0x0604fa09,
|
||||
0xfa060ef4,
|
||||
0x03f80504,
|
||||
0x27f100f8,
|
||||
0x23cf1400,
|
||||
0x1e3fc800,
|
||||
0xf4170bf4,
|
||||
0x21f40132,
|
||||
0x1e3af052,
|
||||
0xf00023d0,
|
||||
0x24d00147,
|
||||
0xcf00f880,
|
||||
0x3dc84023,
|
||||
0x220bf41e,
|
||||
0xf40131f4,
|
||||
0x57f05221,
|
||||
0x0367f004,
|
||||
0xa07856bc,
|
||||
0xb6018068,
|
||||
0x87d00884,
|
||||
0x0162b600,
|
||||
0xf0f018f4,
|
||||
0x23d00237,
|
||||
0xf100f880,
|
||||
0xcf190037,
|
||||
0x33cf4032,
|
||||
0xff24e400,
|
||||
0x1024b607,
|
||||
0x010057f1,
|
||||
0x74bd64bd,
|
||||
0x58005658,
|
||||
0x50b60157,
|
||||
0x0446b804,
|
||||
0xbb4d08f4,
|
||||
0x47b80076,
|
||||
0x0f08f404,
|
||||
0xb60276bb,
|
||||
0x57bb0374,
|
||||
0xdf0ef400,
|
||||
0xb60246bb,
|
||||
0x45bb0344,
|
||||
0x01459800,
|
||||
0xb00453fd,
|
||||
0x1bf40054,
|
||||
0x00455820,
|
||||
0xb0014658,
|
||||
0x1bf40064,
|
||||
0x00538009,
|
||||
0xf4300ef4,
|
||||
0x55f90132,
|
||||
0xf40c01f4,
|
||||
0x25f0250e,
|
||||
0x0125f002,
|
||||
0x100047f1,
|
||||
0xd00042d0,
|
||||
0x27f04043,
|
||||
0x0002d040,
|
||||
0xf08002cf,
|
||||
0x24b04024,
|
||||
0xf71bf400,
|
||||
0x1d0027f1,
|
||||
0xd00137f0,
|
||||
0x00f80023,
|
||||
0x27f100f8,
|
||||
0x34bd2200,
|
||||
0xd00233f0,
|
||||
0x00f80023,
|
||||
0x012842b7,
|
||||
0xf00145b6,
|
||||
0x43801e39,
|
||||
0x0040b701,
|
||||
0x0644b606,
|
||||
0xf80043d0,
|
||||
0xf030f400,
|
||||
0xb00001b0,
|
||||
0x01b00101,
|
||||
0x0301b002,
|
||||
0xc71d0498,
|
||||
0x50b63045,
|
||||
0x3446c701,
|
||||
0xc70160b6,
|
||||
0x70b63847,
|
||||
0x0232f401,
|
||||
0x94bd84bd,
|
||||
0xb60f4ac4,
|
||||
0xb4bd0445,
|
||||
0xf404a430,
|
||||
0xa5ff0f18,
|
||||
0x00cbbbc0,
|
||||
0xf40231f4,
|
||||
0x1bf4220e,
|
||||
0x10c7f00c,
|
||||
0xf400cbbb,
|
||||
0xa430160e,
|
||||
0x0c18f406,
|
||||
0xbb14c7f0,
|
||||
0x0ef400cb,
|
||||
0x80c7f107,
|
||||
0x01c83800,
|
||||
0xb60180b6,
|
||||
0xb5b801b0,
|
||||
0xc308f404,
|
||||
0xb80190b6,
|
||||
0x08f40497,
|
||||
0x0065fdb2,
|
||||
0x98110680,
|
||||
0x68fd2008,
|
||||
0x0502f400,
|
||||
0x75fd64bd,
|
||||
0x1c078000,
|
||||
0xf10078fd,
|
||||
0xb6081057,
|
||||
0x56d00654,
|
||||
0x4057d000,
|
||||
0x080050b7,
|
||||
0xb61c0698,
|
||||
0x64b60162,
|
||||
0x11079808,
|
||||
0xfd0172b6,
|
||||
0x56d00567,
|
||||
0x0050b700,
|
||||
0x0060b401,
|
||||
0xb40056d0,
|
||||
0x56d00160,
|
||||
0x0260b440,
|
||||
0xb48056d0,
|
||||
0x56d00360,
|
||||
0x0050b7c0,
|
||||
0x1e069804,
|
||||
0x980056d0,
|
||||
0x56d01f06,
|
||||
0x1030f440,
|
||||
0x579800f8,
|
||||
0x6879c70a,
|
||||
0xb66478c7,
|
||||
0x77c70280,
|
||||
0x0e76b060,
|
||||
0xf0091bf4,
|
||||
0x0ef40477,
|
||||
0x027cf00f,
|
||||
0xfd1170b6,
|
||||
0x77f00947,
|
||||
0x0f5a9806,
|
||||
0xfd115b98,
|
||||
0xb7f000ab,
|
||||
0x04b7bb01,
|
||||
0xff01b2b6,
|
||||
0xa7bbc4ab,
|
||||
0x105d9805,
|
||||
0xbb01e7f0,
|
||||
0xe2b604e8,
|
||||
0xb4deff01,
|
||||
0xb605d8bb,
|
||||
0xef9401e0,
|
||||
0x02ebbb0c,
|
||||
0xf005fefd,
|
||||
0x60b7026c,
|
||||
0x64b60208,
|
||||
0x006fd008,
|
||||
0xbb04b7bb,
|
||||
0x5f9800cb,
|
||||
0x115b980b,
|
||||
0xf000fbfd,
|
||||
0xb7bb01b7,
|
||||
0x01b2b604,
|
||||
0xbb00fbbb,
|
||||
0xf0f905f7,
|
||||
0xf00c5f98,
|
||||
0xb8bb01b7,
|
||||
0x01b2b604,
|
||||
0xbb00fbbb,
|
||||
0xf0f905f8,
|
||||
0xb60078bb,
|
||||
0xb7f00282,
|
||||
0x04b8bb01,
|
||||
0x9804b9bb,
|
||||
0xe7f00e58,
|
||||
0x04e9bb01,
|
||||
0xff01e2b6,
|
||||
0xf7bbf48e,
|
||||
0x00cfbb04,
|
||||
0xbb0079bb,
|
||||
0xf0fc0589,
|
||||
0xd9fd90fc,
|
||||
0x00adbb00,
|
||||
0xfd0089fd,
|
||||
0xa8bb008f,
|
||||
0x04a7bb00,
|
||||
0xbb0192b6,
|
||||
0x69d00497,
|
||||
0x08579880,
|
||||
0xbb075898,
|
||||
0x7abb00ac,
|
||||
0x0081b600,
|
||||
0xfd1084b6,
|
||||
0x62b7058b,
|
||||
0x67d00600,
|
||||
0x0060b700,
|
||||
0x0068d004,
|
||||
0x6cf000f8,
|
||||
0x0260b702,
|
||||
0x0864b602,
|
||||
0xd0085798,
|
||||
0x60b70067,
|
||||
0x57980400,
|
||||
0x1074b607,
|
||||
0xb70067d0,
|
||||
0x98040060,
|
||||
0x67d00957,
|
||||
0xf900f800,
|
||||
0xf110f900,
|
||||
0xb6080007,
|
||||
0x01cf0604,
|
||||
0x0114f000,
|
||||
0xfcfa1bf4,
|
||||
0xf800fc10,
|
||||
0x0d34c800,
|
||||
0xf5701bf4,
|
||||
0xf103ab21,
|
||||
0xb6080c47,
|
||||
0x05980644,
|
||||
0x0450b605,
|
||||
0xd00045d0,
|
||||
0x57f04040,
|
||||
0x8045d00c,
|
||||
0x040040b7,
|
||||
0xb6040598,
|
||||
0x45d01054,
|
||||
0x0040b700,
|
||||
0x0057f105,
|
||||
0x0153f00b,
|
||||
0xf10045d0,
|
||||
0xb6404057,
|
||||
0x53f10154,
|
||||
0x45d08080,
|
||||
0x1057f140,
|
||||
0x1253f111,
|
||||
0x8045d013,
|
||||
0x151457f1,
|
||||
0x171653f1,
|
||||
0xf1c045d0,
|
||||
0xf0260157,
|
||||
0x47f10153,
|
||||
0x44b60800,
|
||||
0x0045d006,
|
||||
0x03ab21f5,
|
||||
0x080c47f1,
|
||||
0x980644b6,
|
||||
0x45d00505,
|
||||
0x4040d000,
|
||||
0xd00457f0,
|
||||
0x40b78045,
|
||||
0x05980400,
|
||||
0x1054b604,
|
||||
0xb70045d0,
|
||||
0xf1050040,
|
||||
0xd0030057,
|
||||
0x57f10045,
|
||||
0x53f11110,
|
||||
0x45d01312,
|
||||
0x06059840,
|
||||
0x050040b7,
|
||||
0xf10045d0,
|
||||
0xf0260157,
|
||||
0x47f10153,
|
||||
0x44b60800,
|
||||
0x0045d006,
|
||||
0x21f500f8,
|
||||
0x3fc803ab,
|
||||
0x0e0bf400,
|
||||
0x018921f5,
|
||||
0x020047f1,
|
||||
0xf11e0ef4,
|
||||
0xb6081067,
|
||||
0x77f00664,
|
||||
0x11078001,
|
||||
0x981c0780,
|
||||
0x67d02007,
|
||||
0x4067d000,
|
||||
0x32f444bd,
|
||||
0xc854bd02,
|
||||
0x0bf4043f,
|
||||
0x8221f50a,
|
||||
0x0a0ef403,
|
||||
0x027621f5,
|
||||
0xf40749f0,
|
||||
0x57f00231,
|
||||
0x083fc82c,
|
||||
0xf50a0bf4,
|
||||
0xf4038221,
|
||||
0x21f50a0e,
|
||||
0x49f00276,
|
||||
0x0057f108,
|
||||
0x0654b608,
|
||||
0xd0210698,
|
||||
0x67f04056,
|
||||
0x0063f141,
|
||||
0x0546fd44,
|
||||
0xc80054d0,
|
||||
0x0bf40c3f,
|
||||
0xc521f507,
|
||||
0xf100f803,
|
||||
0xbd220027,
|
||||
0x0133f034,
|
||||
0xf80023d0,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user