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drm/i915: Program BXT_CDCLK_CD2X_PIPE
BXT could change the CD2X divider synchronized with a single pipe. So assuming the DE PLL frequency doesn't need to be changed, we could change cdclk without shutting off the pipe (when only a single pipe is enabled). In the meantime let's configure CDCLK_CTL for non-double buffered CD2X update, although it shouldn't really matter as long as the selected pipe is disabled when reprogramming the divider. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1462995892-32416-13-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
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@ -7566,14 +7566,15 @@ enum skl_disp_power_wells {
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#define CDCLK_FREQ_540 (1<<26)
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#define CDCLK_FREQ_337_308 (2<<26)
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#define CDCLK_FREQ_675_617 (3<<26)
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#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
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#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
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#define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
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#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
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#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
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#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
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#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
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#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
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#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
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#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
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/* LCPLL_CTL */
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#define LCPLL1_CTL _MMIO(0x46010)
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@ -5430,6 +5430,11 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
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DRM_ERROR("timeout waiting for DE PLL lock\n");
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val = I915_READ(CDCLK_CTL);
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/*
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* FIXME if only the cd2x divider needs changing, it could be done
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* without shutting off the pipe (if only one pipe is active).
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*/
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val |= BXT_CDCLK_CD2X_PIPE_NONE;
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val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
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val |= divider;
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/*
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