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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 21:00:53 +07:00
EDAC, sb_edac: Don't use "Socket#" in the memory controller name
EDAC assigns logical memory controller numbers in the order that we find memory controllers, which depends on which PCI bus they are on. Some systems end up with MC0 on socket0, others (e.g Haswell) have MC0 on socket3. All this is made more confusing for users because we use the string "Socket" while generating names for memory controllers, but the number that we attach there is the memory controller number. E.g. EDAC MC0: Giving out device to module sbridge_edac.c controller Haswell Socket#0: DEV 0000:ff:12.0 (INTERRUPT) Change the names to say "SrcID#%d" (where the number we use is read from the h/w associated with the memory controller instead of some logical number internal to the EDAC driver). New message: EDAC MC0: Giving out device to module sbridge_edac.c controller Haswell SrcID#3: DEV 0000:ff:12.0 (INTERRUPT) Reported-by: Andrey Korolyov <andrey@xdel.ru> Reported-by: Patrick Geary <patrickg@supermicro.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/20170523000603.87748-1-qiuxu.zhuo@intel.com Signed-off-by: Borislav Petkov <bp@suse.de>
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00cf50d90a
commit
7fd562b75d
@ -1594,6 +1594,23 @@ static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
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return 0;
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}
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static void get_source_id(struct mem_ctl_info *mci)
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{
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struct sbridge_pvt *pvt = mci->pvt_info;
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u32 reg;
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if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
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pvt->info.type == KNIGHTS_LANDING)
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pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
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else
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pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
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if (pvt->info.type == KNIGHTS_LANDING)
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pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
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else
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pvt->sbridge_dev->source_id = SOURCE_ID(reg);
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}
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static int get_dimm_config(struct mem_ctl_info *mci)
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{
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struct sbridge_pvt *pvt = mci->pvt_info;
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@ -1611,17 +1628,6 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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pci_read_config_dword(pvt->pci_ha0, HASWELL_HASYSDEFEATURE2, ®);
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pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
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}
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if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
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pvt->info.type == KNIGHTS_LANDING)
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pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
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else
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pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
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if (pvt->info.type == KNIGHTS_LANDING)
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pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
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else
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pvt->sbridge_dev->source_id = SOURCE_ID(reg);
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pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
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edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
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pvt->sbridge_dev->mc,
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@ -3222,12 +3228,14 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
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pvt->info.interleave_pkg = ibridge_interleave_pkg;
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pvt->info.get_width = ibridge_get_width;
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mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
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/* Store pci devices at mci for faster access */
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rc = ibridge_mci_bind_devs(mci, sbridge_dev);
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if (unlikely(rc < 0))
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goto fail0;
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get_source_id(mci);
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mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d",
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pvt->sbridge_dev->source_id);
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break;
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case SANDY_BRIDGE:
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pvt->info.rankcfgr = SB_RANK_CFG_A;
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@ -3245,12 +3253,14 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
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pvt->info.interleave_pkg = sbridge_interleave_pkg;
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pvt->info.get_width = sbridge_get_width;
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mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
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/* Store pci devices at mci for faster access */
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rc = sbridge_mci_bind_devs(mci, sbridge_dev);
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if (unlikely(rc < 0))
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goto fail0;
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get_source_id(mci);
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mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d",
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pvt->sbridge_dev->source_id);
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break;
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case HASWELL:
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/* rankcfgr isn't used */
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@ -3268,12 +3278,14 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
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pvt->info.interleave_pkg = ibridge_interleave_pkg;
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pvt->info.get_width = ibridge_get_width;
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mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
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/* Store pci devices at mci for faster access */
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rc = haswell_mci_bind_devs(mci, sbridge_dev);
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if (unlikely(rc < 0))
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goto fail0;
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get_source_id(mci);
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mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d",
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pvt->sbridge_dev->source_id);
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break;
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case BROADWELL:
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/* rankcfgr isn't used */
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@ -3291,12 +3303,14 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
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pvt->info.interleave_pkg = ibridge_interleave_pkg;
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pvt->info.get_width = broadwell_get_width;
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mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
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/* Store pci devices at mci for faster access */
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rc = broadwell_mci_bind_devs(mci, sbridge_dev);
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if (unlikely(rc < 0))
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goto fail0;
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get_source_id(mci);
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mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d",
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pvt->sbridge_dev->source_id);
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break;
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case KNIGHTS_LANDING:
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/* pvt->info.rankcfgr == ??? */
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@ -3314,12 +3328,13 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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pvt->info.max_interleave = ARRAY_SIZE(knl_interleave_list);
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pvt->info.interleave_pkg = ibridge_interleave_pkg;
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pvt->info.get_width = knl_get_width;
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mci->ctl_name = kasprintf(GFP_KERNEL,
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"Knights Landing Socket#%d", mci->mc_idx);
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rc = knl_mci_bind_devs(mci, sbridge_dev);
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if (unlikely(rc < 0))
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goto fail0;
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get_source_id(mci);
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mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d",
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pvt->sbridge_dev->source_id);
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break;
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}
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@ -3334,13 +3349,14 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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if (unlikely(edac_mc_add_mc(mci))) {
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edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
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rc = -EINVAL;
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goto fail0;
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goto fail;
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}
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return 0;
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fail0:
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fail:
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kfree(mci->ctl_name);
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fail0:
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edac_mc_free(mci);
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sbridge_dev->mci = NULL;
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return rc;
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