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powerpc/64: Add some more SPRs and SPR bits for POWER9
These definitions will be needed by KVM. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -153,6 +153,8 @@
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#define PSSCR_EC 0x00100000 /* Exit Criterion */
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#define PSSCR_ESL 0x00200000 /* Enable State Loss */
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#define PSSCR_SD 0x00400000 /* Status Disable */
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#define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
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#define PSSCR_GUEST_VIS 0xf0000000000003ff /* Guest-visible PSSCR fields */
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/* Floating Point Status and Control Register (FPSCR) Fields */
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#define FPSCR_FX 0x80000000 /* FPU exception summary */
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@ -236,6 +238,7 @@
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#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
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#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */
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#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
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#define SPRN_TIDR 144 /* Thread ID register */
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#define SPRN_CTRLF 0x088
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#define SPRN_CTRLT 0x098
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#define CTRL_CT 0xc0000000 /* current thread */
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@ -294,6 +297,7 @@
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#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
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#define SPRN_LMRR 0x32D /* Load Monitor Region Register */
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#define SPRN_LMSER 0x32E /* Load Monitor Section Enable Register */
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#define SPRN_ASDR 0x330 /* Access segment descriptor register */
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#define SPRN_IC 0x350 /* Virtual Instruction Count */
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#define SPRN_VTB 0x351 /* Virtual Time Base */
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#define SPRN_LDBAR 0x352 /* LD Base Address Register */
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@ -357,6 +361,7 @@
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#define LPCR_PECE2 ASM_CONST(0x0000000000001000) /* machine check etc can cause exit */
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#define LPCR_MER ASM_CONST(0x0000000000000800) /* Mediated External Exception */
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#define LPCR_MER_SH 11
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#define LPCR_GTSE ASM_CONST(0x0000000000000400) /* Guest Translation Shootdown Enable */
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#define LPCR_TC ASM_CONST(0x0000000000000200) /* Translation control */
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#define LPCR_LPES 0x0000000c
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#define LPCR_LPES0 ASM_CONST(0x0000000000000008) /* LPAR Env selector 0 */
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