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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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net: dsa: bcm_sf2: Move setup function at the far end
Re-order the bcm_sf2_sw_setup() function so that it is at the far end of the driver to avoid any kind of forward declarations. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Florian Fainelli
David S. Miller
parent
a468ef452a
commit
7fbb1a92ef
@ -1065,125 +1065,6 @@ static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
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of_node_put(priv->master_mii_dn);
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}
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static int bcm_sf2_sw_setup(struct dsa_switch *ds)
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{
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const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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struct device_node *dn;
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void __iomem **base;
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unsigned int port;
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unsigned int i;
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u32 reg, rev;
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int ret;
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spin_lock_init(&priv->indir_lock);
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mutex_init(&priv->stats_mutex);
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/* All the interesting properties are at the parent device_node
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* level
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*/
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dn = ds->cd->of_node->parent;
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bcm_sf2_identify_ports(priv, ds->cd->of_node);
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priv->irq0 = irq_of_parse_and_map(dn, 0);
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priv->irq1 = irq_of_parse_and_map(dn, 1);
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base = &priv->core;
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for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
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*base = of_iomap(dn, i);
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if (*base == NULL) {
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pr_err("unable to find register: %s\n", reg_names[i]);
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ret = -ENOMEM;
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goto out_unmap;
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}
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base++;
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}
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ret = bcm_sf2_sw_rst(priv);
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if (ret) {
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pr_err("unable to software reset switch: %d\n", ret);
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goto out_unmap;
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}
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ret = bcm_sf2_mdio_register(ds);
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if (ret) {
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pr_err("failed to register MDIO bus\n");
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goto out_unmap;
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}
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/* Disable all interrupts and request them */
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bcm_sf2_intr_disable(priv);
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ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
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"switch_0", priv);
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if (ret < 0) {
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pr_err("failed to request switch_0 IRQ\n");
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goto out_unmap;
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}
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ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
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"switch_1", priv);
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if (ret < 0) {
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pr_err("failed to request switch_1 IRQ\n");
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goto out_free_irq0;
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}
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/* Reset the MIB counters */
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reg = core_readl(priv, CORE_GMNCFGCFG);
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reg |= RST_MIB_CNT;
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core_writel(priv, reg, CORE_GMNCFGCFG);
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reg &= ~RST_MIB_CNT;
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core_writel(priv, reg, CORE_GMNCFGCFG);
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/* Get the maximum number of ports for this switch */
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priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
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if (priv->hw_params.num_ports > DSA_MAX_PORTS)
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priv->hw_params.num_ports = DSA_MAX_PORTS;
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/* Assume a single GPHY setup if we can't read that property */
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if (of_property_read_u32(dn, "brcm,num-gphy",
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&priv->hw_params.num_gphy))
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priv->hw_params.num_gphy = 1;
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/* Enable all valid ports and disable those unused */
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for (port = 0; port < priv->hw_params.num_ports; port++) {
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/* IMP port receives special treatment */
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if ((1 << port) & ds->enabled_port_mask)
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bcm_sf2_port_setup(ds, port, NULL);
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else if (dsa_is_cpu_port(ds, port))
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bcm_sf2_imp_setup(ds, port);
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else
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bcm_sf2_port_disable(ds, port, NULL);
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}
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rev = reg_readl(priv, REG_SWITCH_REVISION);
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priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
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SWITCH_TOP_REV_MASK;
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priv->hw_params.core_rev = (rev & SF2_REV_MASK);
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rev = reg_readl(priv, REG_PHY_REVISION);
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priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
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pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
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priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
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priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
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priv->core, priv->irq0, priv->irq1);
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return 0;
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out_free_irq0:
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free_irq(priv->irq0, priv);
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out_unmap:
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base = &priv->core;
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for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
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if (*base)
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iounmap(*base);
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base++;
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}
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bcm_sf2_mdio_unregister(priv);
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return ret;
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}
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static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
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{
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return 0;
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@ -1431,6 +1312,125 @@ static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
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return p->ethtool_ops->set_wol(p, wol);
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}
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static int bcm_sf2_sw_setup(struct dsa_switch *ds)
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{
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const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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struct device_node *dn;
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void __iomem **base;
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unsigned int port;
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unsigned int i;
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u32 reg, rev;
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int ret;
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spin_lock_init(&priv->indir_lock);
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mutex_init(&priv->stats_mutex);
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/* All the interesting properties are at the parent device_node
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* level
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*/
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dn = ds->cd->of_node->parent;
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bcm_sf2_identify_ports(priv, ds->cd->of_node);
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priv->irq0 = irq_of_parse_and_map(dn, 0);
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priv->irq1 = irq_of_parse_and_map(dn, 1);
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base = &priv->core;
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for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
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*base = of_iomap(dn, i);
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if (*base == NULL) {
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pr_err("unable to find register: %s\n", reg_names[i]);
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ret = -ENOMEM;
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goto out_unmap;
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}
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base++;
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}
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ret = bcm_sf2_sw_rst(priv);
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if (ret) {
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pr_err("unable to software reset switch: %d\n", ret);
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goto out_unmap;
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}
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ret = bcm_sf2_mdio_register(ds);
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if (ret) {
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pr_err("failed to register MDIO bus\n");
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goto out_unmap;
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}
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/* Disable all interrupts and request them */
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bcm_sf2_intr_disable(priv);
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ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
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"switch_0", priv);
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if (ret < 0) {
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pr_err("failed to request switch_0 IRQ\n");
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goto out_unmap;
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}
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ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
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"switch_1", priv);
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if (ret < 0) {
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pr_err("failed to request switch_1 IRQ\n");
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goto out_free_irq0;
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}
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/* Reset the MIB counters */
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reg = core_readl(priv, CORE_GMNCFGCFG);
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reg |= RST_MIB_CNT;
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core_writel(priv, reg, CORE_GMNCFGCFG);
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reg &= ~RST_MIB_CNT;
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core_writel(priv, reg, CORE_GMNCFGCFG);
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/* Get the maximum number of ports for this switch */
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priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
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if (priv->hw_params.num_ports > DSA_MAX_PORTS)
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priv->hw_params.num_ports = DSA_MAX_PORTS;
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/* Assume a single GPHY setup if we can't read that property */
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if (of_property_read_u32(dn, "brcm,num-gphy",
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&priv->hw_params.num_gphy))
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priv->hw_params.num_gphy = 1;
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/* Enable all valid ports and disable those unused */
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for (port = 0; port < priv->hw_params.num_ports; port++) {
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/* IMP port receives special treatment */
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if ((1 << port) & ds->enabled_port_mask)
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bcm_sf2_port_setup(ds, port, NULL);
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else if (dsa_is_cpu_port(ds, port))
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bcm_sf2_imp_setup(ds, port);
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else
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bcm_sf2_port_disable(ds, port, NULL);
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}
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rev = reg_readl(priv, REG_SWITCH_REVISION);
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priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
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SWITCH_TOP_REV_MASK;
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priv->hw_params.core_rev = (rev & SF2_REV_MASK);
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rev = reg_readl(priv, REG_PHY_REVISION);
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priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
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pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
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priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
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priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
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priv->core, priv->irq0, priv->irq1);
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return 0;
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out_free_irq0:
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free_irq(priv->irq0, priv);
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out_unmap:
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base = &priv->core;
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for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
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if (*base)
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iounmap(*base);
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base++;
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}
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bcm_sf2_mdio_unregister(priv);
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return ret;
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}
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static struct dsa_switch_driver bcm_sf2_switch_driver = {
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.tag_protocol = DSA_TAG_PROTO_BRCM,
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.probe = bcm_sf2_sw_drv_probe,
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