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drm/msm/dpu: move some sspp caps to dpu_caps

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This isn't something that ever changes between planes, so move it to
dpu_caps struct. Making this change will allow more re-use in the
"SSPP sub blocks config" part of the catalog, in particular when adding
support for SM8150 and SM8250 which have different max_linewidth.

This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation
is not supported on the newest DPU versions. (note that decimation is not
implemented, so this changes nothing)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Jonathan Marek 2020-07-10 20:47:26 -04:00 committed by Rob Clark
parent 544d8b9615
commit 7e9d4cdd65
3 changed files with 17 additions and 27 deletions
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14
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View File

@ -70,6 +70,10 @@ static const struct dpu_caps sdm845_dpu_caps = {
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
.max_hdeci_exp = MAX_HORZ_DECIMATION,
.max_vdeci_exp = MAX_VERT_DECIMATION,
};
static const struct dpu_caps sc7180_dpu_caps = {
@ -80,6 +84,8 @@ static const struct dpu_caps sc7180_dpu_caps = {
.ubwc_version = DPU_HW_UBWC_VER_20,
.has_dim_layer = true,
.has_idle_pc = true,
.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
static const struct dpu_mdp_cfg sdm845_mdp[] = {
@ -178,16 +184,9 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
*************************************************************/
/* SSPP common configuration */
static const struct dpu_sspp_blks_common sdm845_sspp_common = {
.maxlinewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
.maxhdeciexp = MAX_HORZ_DECIMATION,
.maxvdeciexp = MAX_VERT_DECIMATION,
};
#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
{ \
.common = &sdm845_sspp_common, \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
.smart_dma_priority = sdma_pri, \
@ -207,7 +206,6 @@ static const struct dpu_sspp_blks_common sdm845_sspp_common = {
#define _DMA_SBLK(num, sdma_pri) \
{ \
.common = &sdm845_sspp_common, \
.maxdwnscale = SSPP_UNITY_SCALE, \
.maxupscale = SSPP_UNITY_SCALE, \
.smart_dma_priority = sdma_pri, \

24
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@ -301,6 +301,10 @@ struct dpu_qos_lut_tbl {
* @has_dim_layer dim layer feature status
* @has_idle_pc indicate if idle power collapse feature is supported
* @has_3d_merge indicate if 3D merge is supported
* @max_linewidth max linewidth for sspp
* @pixel_ram_size size of latency hiding and de-tiling buffer in bytes
* @max_hdeci_exp max horizontal decimation supported (max is 2^value)
* @max_vdeci_exp max vertical decimation supported (max is 2^value)
*/
struct dpu_caps {
u32 max_mixer_width;
@ -312,22 +316,11 @@ struct dpu_caps {
bool has_dim_layer;
bool has_idle_pc;
bool has_3d_merge;
};
/**
* struct dpu_sspp_blks_common : SSPP sub-blocks common configuration
* @maxwidth: max pixelwidth supported by this pipe
* @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes
* @maxhdeciexp: max horizontal decimation supported by this pipe
* (max is 2^value)
* @maxvdeciexp: max vertical decimation supported by this pipe
* (max is 2^value)
*/
struct dpu_sspp_blks_common {
u32 maxlinewidth;
/* SSPP limits */
u32 max_linewidth;
u32 pixel_ram_size;
u32 maxhdeciexp;
u32 maxvdeciexp;
u32 max_hdeci_exp;
u32 max_vdeci_exp;
};
/**
@ -353,7 +346,6 @@ struct dpu_sspp_blks_common {
* @virt_num_formats: Number of supported formats for virtual planes
*/
struct dpu_sspp_sub_blks {
const struct dpu_sspp_blks_common *common;
u32 creq_vblank;
u32 danger_vblank;
u32 maxdwnscale;

6
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
View File

@ -153,7 +153,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
pdpu = to_dpu_plane(plane);
pstate = to_dpu_plane_state(plane->state);
fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size;
fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
if (!tmp->base.state->visible)
@ -709,7 +709,7 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
* So we cannot support more than half of the supported SSPP
* width for tiled formats.
*/
width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth;
width_threshold = dpu_plane[i]->catalog->caps->max_linewidth;
if (has_tiled_rect)
width_threshold /= 2;
@ -887,7 +887,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
fb_rect.x2 = state->fb->width;
fb_rect.y2 = state->fb->height;
max_linewidth = pdpu->pipe_sblk->common->maxlinewidth;
max_linewidth = pdpu->catalog->caps->max_linewidth;
fmt = to_dpu_format(msm_framebuffer_format(state->fb));