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ice: avoid undefined behavior
When writing the driver's struct ice_tlan_ctx structure, do not write the 8-bit element int_q_state with the associated internal-to-hardware field which is 122-bits, otherwise the helper function ice_write_byte() will use undefined behavior when setting the mask used for that write. This should not cause any functional change and will avoid use of undefined behavior. Also, update a comment to highlight this structure element is not written. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -638,6 +638,7 @@ ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring,
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struct ice_aqc_add_txqs_perq *txq;
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struct ice_aqc_add_txqs_perq *txq;
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struct ice_pf *pf = vsi->back;
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struct ice_pf *pf = vsi->back;
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u8 buf_len = sizeof(*qg_buf);
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u8 buf_len = sizeof(*qg_buf);
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struct ice_hw *hw = &pf->hw;
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enum ice_status status;
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enum ice_status status;
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u16 pf_q;
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u16 pf_q;
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u8 tc;
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u8 tc;
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@ -646,13 +647,13 @@ ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring,
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ice_setup_tx_ctx(ring, &tlan_ctx, pf_q);
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ice_setup_tx_ctx(ring, &tlan_ctx, pf_q);
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/* copy context contents into the qg_buf */
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/* copy context contents into the qg_buf */
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qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);
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qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);
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ice_set_ctx((u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx,
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ice_set_ctx(hw, (u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx,
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ice_tlan_ctx_info);
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ice_tlan_ctx_info);
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/* init queue specific tail reg. It is referred as
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/* init queue specific tail reg. It is referred as
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* transmit comm scheduler queue doorbell.
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* transmit comm scheduler queue doorbell.
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*/
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*/
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ring->tail = pf->hw.hw_addr + QTX_COMM_DBELL(pf_q);
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ring->tail = hw->hw_addr + QTX_COMM_DBELL(pf_q);
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if (IS_ENABLED(CONFIG_DCB))
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if (IS_ENABLED(CONFIG_DCB))
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tc = ring->dcb_tc;
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tc = ring->dcb_tc;
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@ -1098,7 +1098,7 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
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rlan_ctx->prefena = 1;
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rlan_ctx->prefena = 1;
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ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
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ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
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return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
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return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
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}
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}
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@ -3199,12 +3199,14 @@ ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
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/**
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/**
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* ice_set_ctx - set context bits in packed structure
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* ice_set_ctx - set context bits in packed structure
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* @hw: pointer to the hardware structure
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* @src_ctx: pointer to a generic non-packed context structure
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* @src_ctx: pointer to a generic non-packed context structure
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* @dest_ctx: pointer to memory for the packed structure
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* @dest_ctx: pointer to memory for the packed structure
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* @ce_info: a description of the structure to be transformed
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* @ce_info: a description of the structure to be transformed
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*/
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*/
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enum ice_status
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enum ice_status
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ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
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ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
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const struct ice_ctx_ele *ce_info)
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{
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{
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int f;
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int f;
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@ -3213,6 +3215,12 @@ ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
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* using the correct size so that we are correct regardless
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* using the correct size so that we are correct regardless
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* of the endianness of the machine.
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* of the endianness of the machine.
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*/
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*/
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if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
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ice_debug(hw, ICE_DBG_QCTX,
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"Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
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f, ce_info[f].width, ce_info[f].size_of);
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continue;
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}
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switch (ce_info[f].size_of) {
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switch (ce_info[f].size_of) {
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case sizeof(u8):
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case sizeof(u8):
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ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
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ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
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@ -70,7 +70,8 @@ enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
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void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
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void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
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extern const struct ice_ctx_ele ice_tlan_ctx_info[];
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extern const struct ice_ctx_ele ice_tlan_ctx_info[];
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enum ice_status
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enum ice_status
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ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);
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ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
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const struct ice_ctx_ele *ce_info);
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extern struct mutex ice_global_cfg_lock_sw;
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extern struct mutex ice_global_cfg_lock_sw;
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@ -581,7 +581,7 @@ struct ice_tlan_ctx {
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u8 drop_ena;
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u8 drop_ena;
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u8 cache_prof_idx;
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u8 cache_prof_idx;
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u8 pkt_shaper_prof_idx;
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u8 pkt_shaper_prof_idx;
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u8 int_q_state; /* width not needed - internal do not write */
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u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */
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};
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};
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/* macro to make the table lines short */
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/* macro to make the table lines short */
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