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net/mlx4_en: Limit the number of TX rings
Limit the number of TX rings per UP by the number of cores in the system. Signed-off-by: Inbar Karmy <inbark@mellanox.com> Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1748,7 +1748,7 @@ static void mlx4_en_get_channels(struct net_device *dev,
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struct mlx4_en_priv *priv = netdev_priv(dev);
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channel->max_rx = MAX_RX_RINGS;
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channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
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channel->max_tx = priv->mdev->profile.max_num_tx_rings_p_up;
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channel->rx_count = priv->rx_ring_num;
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channel->tx_count = priv->tx_ring_num[TX] /
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@ -1777,7 +1777,7 @@ static int mlx4_en_set_channels(struct net_device *dev,
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mutex_lock(&mdev->state_lock);
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xdp_count = priv->tx_ring_num[TX_XDP] ? channel->rx_count : 0;
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if (channel->tx_count * priv->prof->num_up + xdp_count >
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MAX_TX_RINGS) {
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priv->mdev->profile.max_num_tx_rings_p_up * priv->prof->num_up) {
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err = -EINVAL;
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en_err(priv,
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"Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n",
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@ -153,7 +153,7 @@ static void mlx4_en_get_profile(struct mlx4_en_dev *mdev)
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int i;
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params->udp_rss = udp_rss;
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params->num_tx_rings_p_up = mlx4_low_memory_profile() ?
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params->max_num_tx_rings_p_up = mlx4_low_memory_profile() ?
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MLX4_EN_MIN_TX_RING_P_UP :
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min_t(int, num_online_cpus(), MLX4_EN_MAX_TX_RING_P_UP);
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@ -170,8 +170,8 @@ static void mlx4_en_get_profile(struct mlx4_en_dev *mdev)
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params->prof[i].tx_ring_size = MLX4_EN_DEF_TX_RING_SIZE;
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params->prof[i].rx_ring_size = MLX4_EN_DEF_RX_RING_SIZE;
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params->prof[i].num_up = MLX4_EN_NUM_UP_LOW;
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params->prof[i].num_tx_rings_p_up = params->num_tx_rings_p_up;
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params->prof[i].tx_ring_num[TX] = params->num_tx_rings_p_up *
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params->prof[i].num_tx_rings_p_up = params->max_num_tx_rings_p_up;
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params->prof[i].tx_ring_num[TX] = params->max_num_tx_rings_p_up *
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params->prof[i].num_up;
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params->prof[i].rss_rings = 0;
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params->prof[i].inline_thold = inline_thold;
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@ -3305,7 +3305,7 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
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priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
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priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
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MLX4_WQE_CTRL_SOLICITED);
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priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
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priv->num_tx_rings_p_up = mdev->profile.max_num_tx_rings_p_up;
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priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
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netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
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@ -399,7 +399,7 @@ struct mlx4_en_profile {
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u32 active_ports;
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u32 small_pkt_int;
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u8 no_reset;
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u8 num_tx_rings_p_up;
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u8 max_num_tx_rings_p_up;
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struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
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};
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