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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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staging: tidspbridge: ioremap dsp sync addr
Change the type of sync_addr to 'void __iomem *' and ioremap the physical address in the shared memory so we can access it using _raw_*. While at it, drop 'dw_' prefix. Fix the warning associated with dsp's sync_addr: warning: passing argument 2 of '__raw_writel' makes pointer from integer without a cast ../io.h:88: note: expected 'volatile void *' but argument is of type 'u32' Signed-off-by: Omar Ramirez Luna <omar.ramirez@copitl.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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3c8676967b
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7de8a0cf48
@ -126,7 +126,8 @@ static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
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u32 ul_num_bytes,
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u32 ul_num_bytes,
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struct hw_mmu_map_attrs_t *hw_attrs);
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struct hw_mmu_map_attrs_t *hw_attrs);
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bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
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bool wait_for_start(struct bridge_dev_context *dev_context,
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void __iomem *sync_addr);
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/* ----------------------------------- Globals */
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/* ----------------------------------- Globals */
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@ -363,10 +364,11 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
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{
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{
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int status = 0;
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int status = 0;
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struct bridge_dev_context *dev_context = dev_ctxt;
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struct bridge_dev_context *dev_context = dev_ctxt;
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u32 dw_sync_addr = 0;
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void __iomem *sync_addr;
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u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
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u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
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u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
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u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
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u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
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u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
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u32 shm_sync_pa;
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/* Offset of shm_base_virt from tlb_base_virt */
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/* Offset of shm_base_virt from tlb_base_virt */
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u32 ul_shm_offset_virt;
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u32 ul_shm_offset_virt;
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s32 entry_ndx;
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s32 entry_ndx;
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@ -397,15 +399,22 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
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/* Kernel logical address */
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/* Kernel logical address */
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ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
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ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
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/* SHM physical sync address */
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shm_sync_pa = dev_context->atlb_entry[0].gpp_pa + ul_shm_offset_virt +
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SHMSYNCOFFSET;
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/* 2nd wd is used as sync field */
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/* 2nd wd is used as sync field */
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dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
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sync_addr = ioremap(shm_sync_pa, SZ_32);
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if (!sync_addr)
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return -ENOMEM;
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/* Write a signature into the shm base + offset; this will
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/* Write a signature into the shm base + offset; this will
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* get cleared when the DSP program starts. */
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* get cleared when the DSP program starts. */
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if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
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if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
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pr_err("%s: Illegal SM base\n", __func__);
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pr_err("%s: Illegal SM base\n", __func__);
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status = -EPERM;
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status = -EPERM;
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} else
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} else
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__raw_writel(0xffffffff, dw_sync_addr);
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__raw_writel(0xffffffff, sync_addr);
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if (!status) {
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if (!status) {
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resources = dev_context->resources;
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resources = dev_context->resources;
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@ -419,8 +428,10 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
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* function is made available.
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* function is made available.
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*/
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*/
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void __iomem *ctrl = ioremap(0x48002000, SZ_4K);
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void __iomem *ctrl = ioremap(0x48002000, SZ_4K);
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if (!ctrl)
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if (!ctrl) {
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iounmap(sync_addr);
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return -ENOMEM;
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return -ENOMEM;
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}
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(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
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(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
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OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
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OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
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@ -588,15 +599,15 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
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(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
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(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
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OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr);
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dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", *(u32 *)sync_addr);
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dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr);
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dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr);
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if (dsp_debug)
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if (dsp_debug)
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while (__raw_readw(dw_sync_addr))
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while (__raw_readw(sync_addr))
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;
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;
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/* Wait for DSP to clear word in shared memory */
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/* Wait for DSP to clear word in shared memory */
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/* Read the Location */
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/* Read the Location */
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if (!wait_for_start(dev_context, dw_sync_addr))
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if (!wait_for_start(dev_context, sync_addr))
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status = -ETIMEDOUT;
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status = -ETIMEDOUT;
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dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en);
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dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en);
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@ -612,7 +623,7 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
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/* Write the synchronization bit to indicate the
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/* Write the synchronization bit to indicate the
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* completion of OPP table update to DSP
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* completion of OPP table update to DSP
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*/
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*/
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__raw_writel(0XCAFECAFE, dw_sync_addr);
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__raw_writel(0XCAFECAFE, sync_addr);
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/* update board state */
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/* update board state */
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dev_context->brd_state = BRD_RUNNING;
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dev_context->brd_state = BRD_RUNNING;
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@ -621,6 +632,9 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
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dev_context->brd_state = BRD_UNKNOWN;
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dev_context->brd_state = BRD_UNKNOWN;
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}
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}
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}
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}
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iounmap(sync_addr);
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return status;
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return status;
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}
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}
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@ -1796,12 +1810,13 @@ static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
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* ======== wait_for_start ========
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* ======== wait_for_start ========
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* Wait for the singal from DSP that it has started, or time out.
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* Wait for the singal from DSP that it has started, or time out.
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*/
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*/
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bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr)
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bool wait_for_start(struct bridge_dev_context *dev_context,
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void __iomem *sync_addr)
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{
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{
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u16 timeout = TIHELEN_ACKTIMEOUT;
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u16 timeout = TIHELEN_ACKTIMEOUT;
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/* Wait for response from board */
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/* Wait for response from board */
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while (__raw_readw(dw_sync_addr) && --timeout)
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while (__raw_readw(sync_addr) && --timeout)
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udelay(10);
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udelay(10);
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/* If timed out: return false */
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/* If timed out: return false */
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